Senior SoC Verification Engineer - Hybrid & Flexible

OPENCHIP & SOFTWARE TECHNOLOGIES; Barcelona; Híbrido; EUR 55.000 - 75.000; Jornada completa

Descripción de la vacante

Openchip & Software Technologies S.L. in Barcelona is seeking a Functional Verification Engineer to interface with architecture, design, hardware and software teams to ensure top-level system performance.

You will develop verification environments in SystemVerilog/UVM, SystemC/C++, and run verification plans, regressions and debugging; contribute to coverage and methodology improvements. The role is based in Barcelona with hybrid work options.

Formación

• Master degree in a relevant field.
• 5+ years of experience in verification of complex SoC/IP.
• Proficiency in SystemVerilog/UVM and SystemC/C++ for verification environments.
• Experience with constrained random, functional coverage, and design debugging.
• Experience in Formal Verification (UPF) and HW-SW co-verification.

Responsabilidades

• Read system requirements and architecture documents to develop verification environments in SystemVerilog/UVM/SystemC/C++, including Stimulus, Checkers, Assertions, Trackers, and Coverage.
• Execute verification plans, bring-up DV environments, run regressions, and debug failures with cross-functional teams.
• Create and execute test cases to verify functionality, performance, and robustness in embedded C and SV.
• Perform coverage analysis, bug tracking, and regression testing to ensure verification quality.
• Contribute to verification methodology improvements.

Conocimientos

English proficiency

SystemVerilog/UVM

SystemC/C++

Constrained random

Functional Coverage

Design debugging

Educación

Master Degree in relevant field

Herramientas

SystemVerilog

UVM

SystemC

Embedded C

Bash/Perl/Python scripting

Descripción del empleo

Openchip & Software Technologies S.L. in Barcelona is seeking a Functional Verification Engineer to interface with architecture, design, hardware and software teams to ensure top-level system performance.

You will develop verification environments in SystemVerilog/UVM, SystemC/C++, and run verification plans, regressions and debugging; contribute to coverage and methodology improvements. The role is based in Barcelona with hybrid work options.