Research Engineer - RTL OoO Core (RISC-V) | Flexible Hours

Barcelona Supercomputing Center; Barcelona; Presencial; EUR 65.000 - 95.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Restaurant tickets

Private health insurance

Relocation support

Descripción de la vacante

Barcelona Supercomputing Center seeks a Research Engineer to advance RTL OoO core development within the DARE project. You will design and verify RISC-V processor techniques and integrate new capabilities into a scalable core.

The role requires strong SystemVerilog, Computer Architecture knowledge, and experience with Linux, Git, and Python-based verification. You will collaborate across teams, document results, and contribute to state-of-the-art HPC infrastructure.

Formación

• BS or MS in Telecommunication, Electronics, Computer Science, or Computer Engineering.
• Logic Circuit Design Knowledge.
• Proficiency in SystemVerilog.
• Computer architecture Knowledge.
• Familiarity with RISC-V Specification.
• Git version control system Knowledge.
• Python and CoCoTB.
• Proficiency with standard open-source tools for RTL simulation.
• Direct Programming Interface for HW Modeling and Host Interfacing.
• Make, Bash, Docker.
• Knowledge in C/C++ and Linux.
• Strong English communication, teamwork and problem solving.

Responsabilidades

• Research of computer architectural techniques and development of RTL hardware structures related to superscalar OoO core design to improve efficiency, scalability, and performance of a current RISC-V core.
• Review and analyze state-of-the-art performance techniques for OoO processor architectures.
• Design RTL structures by implementing selected techniques for RISC-V CPU architectures using SystemVerilog.
• Integrate new capabilities into the RISC-V core with configurable options and performance tradeoffs.
• Develop verification strategy with CoCoTB and Python hardware modeling; implement tests and validation procedures.
• Evaluate impact via simulation and benchmarking; report performance improvements.
• Follow code standards; document specifications, microarchitecture, and test plans.
• Develop and maintain scripts/tools to automate design and verification; contribute to methodologies.
• Ensure high-quality, maintainable RTL code; perform peer reviews and feedback.
• Ensure compliance with industry standards and project guidelines.

Conocimientos

Logic Circuit Design

Computer architecture

Familiarity with RISC-V

Git version control

Python

CoCoTB

SystemVerilog

RTL simulation tools

C/C++ programming

Linux

Make, Bash, Docker

Educación

BS or MS in Telecommunication, Electronics, Computer Science, or Computer Engineering

Herramientas

SystemVerilog

RISC-V

Git

Python

CoCoTB

Linux

Docker

Make

Descripción del empleo

Barcelona Supercomputing Center seeks a Research Engineer to advance RTL OoO core development within the DARE project. You will design and verify RISC-V processor techniques and integrate new capabilities into a scalable core.

The role requires strong SystemVerilog, Computer Architecture knowledge, and experience with Linux, Git, and Python-based verification. You will collaborate across teams, document results, and contribute to state-of-the-art HPC infrastructure.