Senior SERDES/C2C First-Silicon Bring-Up Engineer

Semidynamics; Barcelona; Presencial; EUR 70.000 - 95.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Competitive package

Descripción de la vacante

Semidynamics is seeking an experienced Senior SERDES/C2C First-Silicon Bring-Up Engineer to support the transition from verification collateral to a deterministic, executable and diagnosable physical bring-up flow. The engineer must isolate failures across the physical PHY/modem, clocking and calibration layers and the digital C2C/controller layer.

Work includes collaborating with hardware, firmware and verification teams, bringing up reference clocks, calibration routines and link-training

Formación

• Hands-on first-silicon SERDES or high-speed PHY bring-up experience.
• Strong understanding of PLL, CDR, reference-clock selection, reset sequencing, calibration and lane readiness.
• Experience with TX/RX configuration, termination, equalization, polarity/lane configuration and link-training.
• Ability to debug a link using status registers, counters and physical measurements.
• Low-level C/C++ firmware development, MMIO/register programming and bounded polling/error handling.
• Ability to correlate RTL/UVM/cosimulation collateral with physical-silicon behaviour.
• Practical use of oscilloscopes and related high-speed lab equipment.
• Experience across hardware, firmware and verification teams during first-silicon debug.

Responsabilidades

• Review and reconcile existing verification sequences with the physical bring-up contract.
• Help establish reference-clock, reset, physical-modem, calibration, controller and link-training ordering.
• Implement or review low-level C/C++ register sequences and status polling.
• Define bounded timeout, readback and failure-classification behaviour.
• Execute and debug physical link bring-up with the internal technical owner.
• Use link status, counters and real data to distinguish PHY readiness from functional-link readiness.
• Produce repeatable logs, register snapshots and failure evidence for regression and traceability.

Conocimientos

First-silicon bring-up

PLL/CDR

Reference clock selection

Reset sequencing

Calibration

Lane readiness

TX/RX config

Termination

Equalization

Lane configuration

Link-training

Link debugging

C/C++ firmware

MMIO

Register programming

Polling/error handling

RTL/UVM correlation

Oscilloscopes

Cross-team collaboration

C2C interface

Cadence PHY IP

PHY firmware

Deterministic bring-up

Herramientas

Cadence PHY IP

Oscilloscopes

Descripción del empleo

SelectLevel

ID: CSBE-1

Description

Role Overview
Semidynamics is seeking an experienced Senior SERDES/C2C First-Silicon Bring-Up Engineer to support the transition from verification collateral to a deterministic, executable and diagnosable physical SERDES/C2C bring-up flow. The engineer must be able to isolate failures across the physical PHY/modem, clocking and calibration layers and the digital C2C/controller layer.
Why Semidynamics?

• Work for one of Europe’s most promising deep-tech semiconductor scale-ups.
• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 day WFH.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.

Requirements

Required experience

• Demonstrable hands-on first-silicon SERDES or high-speed PHY bring-up experience.
• Strong understanding of PLL, CDR, reference-clock selection, reset sequencing, calibration and lane readiness.
• Experience with TX/RX configuration, termination, equalization, polarity/lane configuration and link-training flows.
• Ability to debug a link that does not reach its expected operational state using status registers, counters and physical measurements.
• Low-level C/C++ firmware development, MMIO/register programming and bounded polling/error handling.
• Ability to correlate RTL/UVM/cosimulation collateral with physical-silicon behaviour without blindly copying simulation assumptions.
• Practical use of oscilloscopes and appropriate high-speed/debug laboratory equipment.
• Experience working across hardware, firmware and verification teams during first-silicon debug.

Strongly preferred

• Chip-to-chip, chiplet, die-to-die or similar C2C interface experience.
• Experience with Cadence SERDES/PHY IP or comparable commercial PHY IP.
• Experience with PHY firmware, embedded PHY microcontrollers, calibration firmware or mailbox/control interfaces.
• Experience building deterministic bring-up gates and reusable evidence rather than one-off laboratory procedures.

Expected responsibilities

• Review and reconcile existing verification/simulation sequences with the physical bring-up contract.
• Help establish reference-clock, reset, physical-modem, calibration, controller and link-training ordering.
• Implement or review low-level C/C++ register sequences and status polling.
• Define bounded timeout, readback and failure-classification behaviour.
• Execute and debug physical link bring-up together with the internal technical owner.
• Use link status, retry/error counters and a real data transaction to distinguish PHY readiness from functional-link readiness.
• Produce repeatable logs, register snapshots and failure evidence suitable for regression and management traceability.