Senior Digital IC Design Engineer

TMRW; Barcelona; On-site; EUR 60,000 - 90,000; Full time

Job summary

The TMRW Foundation SILICON in Barcelona, Spain is seeking a skilled Digital IC Designer to join our engineering team and deliver disruptive digital ICs. You will design, simulate, and verify complex chips using Cadence tools to meet performance, power, and area targets.

Ideal candidates will have hands-on RTL design (Verilog/VHDL), strong CADENCE experience, and a track record of successful projects. Collaboration with architects, layout engineers, and testers is essential for this role.

Qualifications

• Bachelor's or master's degree in Electrical/Computer Engineering with focus on VLSI or microelectronics.
• Proven experience in digital IC design with a strong project portfolio.
• Expertise in the Cadence digital design flow and tools.
• Familiarity with Synopsys/Mentor tools is a plus.
• Proficiency in Verilog and VHDL and understanding of HDLs.

Responsibilities

• RTL Design & Development: implement RTL code using VHDL/Verilog per specs.
• Simulation & Verification: verify IC designs with Cadence tools (NC Launch/Incisive, SimVision).
• Synthesis & Implementation: floorplanning, placement, clock tree, routing with Genus/Innovus.
• Timing Analysis & Signoff: perform STA with Tempus to meet timing requirements.
• Physical Verification: DRC/LVS checks using Pegasus/Innovus for fabrication readiness.
• Collaboration: work with system architects, analog designers, and layout engineers.
• Documentation: create design docs, reports, and test plans.

Skills

RTL Design

Verilog

VHDL

Digital IC Design

CADENCE

Timing Closure

Scripting (Tcl/Python)

Collaboration

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in Electrical/Computer Engineering

Tools

Cadence Virtuoso

Cadence Genus

Cadence Innovus

Cadence Tempus

SimVision

NC-Launch/Incisive

Pegasus

Job description

The TMRW Foundation SILICON in Barcelona, Spain is seeking a skilled Digital IC Designer to join our engineering team and deliver disruptive digital ICs. You will design, simulate, and verify complex chips using Cadence tools to meet performance, power, and area targets.

Ideal candidates will have hands-on RTL design (Verilog/VHDL), strong CADENCE experience, and a track record of successful projects. Collaboration with architects, layout engineers, and testers is essential for this role.