Senior Analog & Mixed-Signal IC Design Engineer

FLIR Systems, Inc.; Sevilla; Híbrido; EUR 60.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Hybrid work model

Structured onboarding

Free coffee & fruit in office

Career development

Descripción de la vacante

Teledyne Sevilla seeks a seasoned IC Design Engineer to contribute to analog and mixed-signal system development, including transistor-level design and verification. You will define architectures, model signals with HDL, and validate silicon through comprehensive simulations.

Requirements include 3+ years in analog IC design with CMOS tech, plus 2+ years using Cadence tools like Virtuoso/Spectre/PVS/Calibre. Hybrid work in Seville, Spain is offered.

Formación

• Degree in Telecommunications Engineering (Electronics specialization).
• Electronics Engineering degree or Physics with Electronics specialization.
• Master in Microelectronics.
• 3+ years transistor-level analog IC design experience.
• 2+ years Cadence EDA tools experience (Virtuoso/Spectre/PVS/Calibre).

Responsabilidades

• Contribute to all phases of the development of high-performance analog and mixed-signal systems.
• Define architectures, specifications, and models (HDL); perform transistor-level design and simulations.
• Develop test platforms and execute block-, chip-, and system-level circuit simulations for verification.
• Execute tests in the verification plan and report issues to the Technical Director.

Conocimientos

Analog IC design

CMOS tech

DSP algorithms

Cadence tools

Layout & verification

SoC software

Educación

Telecommunications Engineering

Electronics Engineering

Physics (EE)

Electronic Engineering

Microelectronics (Masters)

Herramientas

Cadence Virtuoso

Spectre

PVS

Calibre

Descripción del empleo

Teledyne Sevilla seeks a seasoned IC Design Engineer to contribute to analog and mixed-signal system development, including transistor-level design and verification. You will define architectures, model signals with HDL, and validate silicon through comprehensive simulations.

Requirements include 3+ years in analog IC design with CMOS tech, plus 2+ years using Cadence tools like Virtuoso/Spectre/PVS/Calibre. Hybrid work in Seville, Spain is offered.