Senior ASIC/FPGA Backend Engineer

ARQUIMEA; Madrid; Presencial; EUR 90.000 - 130.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

On-site position at headquarters

Descripción de la vacante

ARQUIMEA is seeking an experienced engineer to lead backend ASIC/FPGA design efforts on-site in Madrid. You will own backend flows, perform timing analysis, and drive sign-off activities while coordinating with frontend RTL teams and analog designers.

The role emphasizes deep knowledge of digital implementation, clocking strategies, and power integrity in a demanding, collaborative environment in Madrid.

Formación

• Telecommunications or electronic engineering background with a master in micro-electronics.
• At least 5 years of backend ASIC/FPGA design experience.
• Experience with digital implementation flows and timing closure.

Responsabilidades

• Own and execute backend implementation flows for ASIC and/or FPGA designs.
• Perform logic synthesis, constraints development, optimization, and design quality checks.
• Run place and route flows including floorplanning, placement, and routing.
• Drive static timing analysis and timing closure across modes and corners.
• Analyze timing, congestion, area, power, and signal integrity issues.
• Develop and maintain timing constraints (SDC/XDC).
• Support backend sign-off activities like DRC/LVS and CDC/RDC.
• Collaborate with analog/design teams for mixed-signal integration.
• Work with FPGA flows: synthesis, implementation, timing analysis, bitstream, bring-up.

Conocimientos

ASIC backend

FPGA backend

Scripting Tcl

Scripting Python

Timing analysis

Place & route

Clocking strategies

Power integrity

Digital design flows

Educación

Telecommunications engineering

Electronic engineering

Master in micro-electronics

Herramientas

Synopsys

Cadence

Siemens EDA

Xilinx Vivado

Intel Quartus

Descripción del empleo

ARQUIMEA is seeking an experienced engineer to lead backend ASIC/FPGA design efforts on-site in Madrid. You will own backend flows, perform timing analysis, and drive sign-off activities while coordinating with frontend RTL teams and analog designers.

The role emphasizes deep knowledge of digital implementation, clocking strategies, and power integrity in a demanding, collaborative environment in Madrid.