Principle High Speed AMS IC Design Engineer

Chipright Inc.; Comunidad de Madrid; On-site; EUR 90,000 - 120,000; Full time

Job summary

Chipright Inc. seeks a Senior Analog Mixed Signal Design Engineer to lead the definition, design, and development of high-speed analog/mixed-signal ICs. The role focuses on full-custom IP blocks in sub-nanometer CMOS and silicon-ready designs, collaborating with a team in R&D to push the next generation of products.

Ideal candidates have 8–10 years in the field, fluency in English, and can operate within EU regulations. EU passport holders are welcome to apply, and the position is based in Spain.

Qualifications

• Degree/Master/PhD in Electronic Engineering.
• 8–10 years in Analog Mixed-Signal design for high speed communications.
• Experience with ADCs, DACs and PLLs.
• Experience delivering silicon-ready designs from definition to qualification.
• Proficiency in full-custom analog IP design in 65nm CMOS or below.
• Schematic to verified layout in nanometric CMOS processes.
• Strong analog layout knowledge and peer-review capability.
• Excellent written and verbal English.

Skills

Analog design

Mixed-signal design

High speed design

ADC blocks

DAC blocks

PLLs

Analog IPs

65nm CMOS

Cadence

Synopsys

Education

Electronic Engineering

Tools

Cadence

Synopsys

Job description

Senior Analog Mixed Signal Design Engineer

Chipright is looking for a Principle High Speed Mixed-Signal IC Design Engineer. As a member of the mixed-signal design team in the R&D department of the company, you will be a key part in the definition, design and development of the future products of the company.

Requirements:

• Degree/Master/PhD in Electronic Engineer.
• At least 8 to 10 years of experience in Analog Mixed Signal Design, specifically in High Speed Communications
• Experience working on blocks such as ADCs, DACs, PLLs
• Experience in delivering successful design in silicon: product definition, characterization, qualification and productization.
• Experience on designing full-custom analog IP blocks in sub-nanometric CMOS technology (65nm or below), as well as with analog and mixed-signal IC design tools, such us Cadence or Synopsys.
• Design (from schematic to full verification at extracted level) of the analog and mixed-signal blocks in nanometric CMOS processes.
• Good knowledge of full-custom analog layout techniques, including the ability to review the work of others.
• Excellent written and verbal English communication skills.

Position is open to EU Passport Holders.