Senior Analog & Mixed-Signal IC Design Engineer

FLIR Systems, Inc.; Sevilla; Presencial; EUR 60.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Hybrid work model

Onboarding program

Coffee and fruit in office

Descripción de la vacante

Teledyne Sevilla seeks an experienced engineer to contribute to the development of high-performance analog and mixed-signal systems. You will define architectures, specifications, models, and perform transistor-level design and simulations using HDL/Verilog and layout.

You will also develop test platforms and run block- and chip-level verifications. The role requires extensive analog IC design experience, DSP knowledge, and Cadence tool proficiency, with a hybrid work arrangement and strong

Formación

• Design, analysis, simulation, layout and verification of analog and mixed-signal circuits.
• Experience with DSP algorithms, FIR filters, windowing, decimation and modulation.
• 3+ years transistor-level analog IC design, preferably CMOS.
• 2+ years Cadence EDA tool experience (Virtuoso/Spectre/PVS/Calibre).
• Experience with layout and physical verification.

Responsabilidades

• Contribute to all phases of development of high-performance analog/mixed-signal systems.
• Define architectures, specifications and models; perform transistor-level design and simulations.
• Develop test platforms and run circuit simulations for verification.
• Execute verification tests and report issues to the Technical Director.

Conocimientos

Analog circuit

Digital circuit

CMOS technology

SoC software

Educación

Telecommunications Engineering or Electronics degree

Master in Microelectronics

Herramientas

Cadence Virtuoso

Cadence Spectre

PVS

Calibre

Descripción del empleo

Teledyne Sevilla seeks an experienced engineer to contribute to the development of high-performance analog and mixed-signal systems. You will define architectures, specifications, models, and perform transistor-level design and simulations using HDL/Verilog and layout.

You will also develop test platforms and run block- and chip-level verifications. The role requires extensive analog IC design experience, DSP knowledge, and Cadence tool proficiency, with a hybrid work arrangement and strong