Senior AMS DV Engineer — Mixed-Signal Verification Leader

Analog Devices, Inc.; España; On-site; EUR 43,000 - 62,000; Full time

Job summary

Analog Devices, Inc. in Valencia, Spain seeks a Senior AMS Design Verification Engineer to join the Custom Silicon Solutions Group and drive mixed-signal verification across a multi-site team. You will contribute to verification strategy and mentor junior members in AMS methodologies.

Applicants should have 5+ years of experience in SOC AMS verification, with UVM, Cadence tools, SVRNM or Verilog-AMS, and scripting. Some travel is expected while compensation includes a discretionary bonus.

Qualifications

• Minimum 5 years of chip-level AMS verification experience.
• Familiarity with UVM and digital mixed-signal verification approaches.
• Proficiency with Cadence-based flows and SVRNM/Verilog-AMS for analog blocks.

Responsibilities

• Act as a mixed-signal verification team member in a multi-site group.
• Contribute to verification strategy and method improvements.
• Develop directed tests in AMS environments and track defects in Jira.

Skills

AMS verification

UVM

Python scripting

Scripting languages

Debugging

Education

Electronic Engineering degree

Tools

Cadence AMS

Verilog-AMS

Cadence flow

Scripting (Python)

Job description

Analog Devices, Inc. in Valencia, Spain seeks a Senior AMS Design Verification Engineer to join the Custom Silicon Solutions Group and drive mixed-signal verification across a multi-site team. You will contribute to verification strategy and mentor junior members in AMS methodologies.

Applicants should have 5+ years of experience in SOC AMS verification, with UVM, Cadence tools, SVRNM or Verilog-AMS, and scripting. Some travel is expected while compensation includes a discretionary bonus.