Senior FPGA/ASIC Logic Design Engineer - Hybrid (Spain)

Ciklum; España; Ibrido; EUR 70.000 - 90.000; Tempo pieno

Vantaggi offerti da questo lavoro

Medical insurance

Udemy license

Company-paid certifications

Language courses

23 vacation days

Short Fridays

Internal Mobility Program

Descrizione del lavoro

Ciklum in Spain is seeking a Senior Logic Design Engineer to join our cross-functional team and help build next-generation FPGA/ASIC platforms for demanding realtime applications.

You will design and optimize low-latency SystemVerilog RTL, work with system architects, verification, software and hardware specialists in an international environment, and drive the RTL development lifecycle from architecture to verification.

Competenze

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of FPGA/ASIC digital logic design experience.
• Strong SystemVerilog RTL development and debugging skills.

Mansioni

• Design and implement complex, low-latency RTL modules using SystemVerilog.
• Develop RTL for FPGA/ASIC applications with timing and power constraints.
• Collaborate with architects, verification, software and hardware teams in an international environment.

Conoscenze

SystemVerilog RTL

RTL design

CDC awareness

FPGA/ASIC workflows

Debugging

Verification

Python/Tcl scripting

English communication

AMD/Xilinx Versal

DSP/waveform generation

Formazione

Electrical/Computer Engineering degree

Strumenti

Vivado

Synopsys VCS

Questa

Descrizione del lavoro

Ciklum in Spain is seeking a Senior Logic Design Engineer to join our cross-functional team and help build next-generation FPGA/ASIC platforms for demanding realtime applications.

You will design and optimize low-latency SystemVerilog RTL, work with system architects, verification, software and hardware specialists in an international environment, and drive the RTL development lifecycle from architecture to verification.