Senior FPGA/ASIC Logic Engineer | Hybrid & Flexible

Ciklum; Málaga; Hybrid; EUR 55,000 - 85,000; Full time

Benefits offered by this job

Medical insurance

Udemy license

Language courses

23 vacation days

Job summary

Ciklum, based in Málaga, is seeking a Senior Logic Design Engineer to join our cross-functional team. You will design and optimize RTL for FPGA/ASIC platforms, supporting advanced control systems and quantum-related projects in an international engineering environment.

You will own SystemVerilog RTL development from architecture to verification, collaborating with system architects, verification engineers, software developers, and hardware specialists to meet stringent latency and timing

Qualifications

• 4+ years of professional FPGA/ASIC digital logic design.
• Proficiency in SystemVerilog RTL development.
• Experience with timing analysis and optimization.
• Experience with hardware-software interfaces and cross-functional teams.

Responsibilities

• Design and implement complex, configurable, low-latency RTL modules using SystemVerilog.
• Develop digital logic for high-performance FPGA and ASIC applications, including signal processing, waveform generation, and real-time control.
• Participate in the complete RTL development lifecycle, from architecture and microarchitecture definition to implementation and verification.
• Optimize RTL designs for timing, latency, resource utilization, and power efficiency.
• Perform logic synthesis, static timing analysis (STA), and optimization to meet design constraints.
• Collaborate with verification engineers to ensure functional correctness and comprehensive test coverage.
• Analyze system-level and software requirements and implement appropriate hardware-software interfaces.
• Integrate proprietary digital IP into complex FPGA/ASIC architectures.
• Participate in design reviews, debugging, and continuous improvement of engineering processes.

Skills

SystemVerilog

RTL development

FPGA/ASIC design

Timing optimization

STA

Debugging

English communication

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

AMD/Xilinx FPGA platforms

Vivado

Synopsys VCS

Questa

Python

Tcl

Job description

Ciklum, based in Málaga, is seeking a Senior Logic Design Engineer to join our cross-functional team. You will design and optimize RTL for FPGA/ASIC platforms, supporting advanced control systems and quantum-related projects in an international engineering environment.

You will own SystemVerilog RTL development from architecture to verification, collaborating with system architects, verification engineers, software developers, and hardware specialists to meet stringent latency and timing