Senior Signal Integrity Engineer

Hireroo Ltd; Barcelona; Hybrid; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Flexible working hours

Hybrid model: 4 days in office, 1 day

Relocation bonus

Housing search support

Visa support if required

Private medical insurance

Language classes

Virtual shares

Job summary

Hireroo Ltd. in Barcelona, Spain, is seeking a Senior Signal Integrity Engineer to own SI across package, board and system interconnects for advanced compute hardware.

This senior IC/IC-RTL style role involves defining budgets and constraints and collaborating with package, PCB, PHY, memory and system teams. Responsibilities include defining loss budgets, performing pre-layout studies, guiding routing and stackup decisions, running 3D EM extraction, and coordinating model quality with vendors.

Qualifications

• 8+ years of signal integrity experience.
• Background in high speed digital systems.
• Strong package level SI experience.
• 3D EM extraction experience.
• Proficiency with HFSS, SIwave, Clarity, Sigrity or equivalent tools.
• Proven SerDes channel closure experience.
• PCIe Gen5/Gen6 or comparable interface experience.
• DDR5, LPDDR5, LPDDR6 or HBM experience.
• Strong IBIS and IBIS AMI knowledge.
• Channel simulation experience.
• Ability to analyse substrate stackups and bump maps.
• Strong understanding of loss, crosstalk, jitter and channel behaviour.
• Python scripting for automation and analysis.

Responsibilities

• Own signal integrity from silicon package through board and system channel
• Define loss, crosstalk and jitter budgets
• Perform pre layout feasibility studies
• Guide routing, stackup and layer assignment
• Run 3D EM extraction of package and board structures
• Perform statistical and time domain channel simulation
• Own PCIe Gen6 channel design and compliance margining
• Support LPDDR interface timing and bus level closure
• Define model quality requirements for passivity, causality and DC accuracy
• Set SI requirements for package, OSAT and component vendors
• Coordinate models with PHY, DRAM and package suppliers
• Correlate simulations with VNA, TDR and silicon measurements
• Support board bring up and SI debug
• Automate analysis and post processing with Python

Skills

Signal Integrity

High-speed digital

Package SI

3D EM Extraction

SI Tools

SerDes Closure

PCIe Gen5/6

Memory Interfaces

IBIS/AMI

Channel Simulation

Stackup Analysis

Loss Crosstalk Jitter

Python scripting

Tools

HFSS

SIwave

Clarity

Sigrity

Keysight

Job description

Job Description

Our partner is looking for a Senior Signal Integrity Engineer to own signal integrity across package, board and system level interconnects for advanced compute hardware.

This is a senior individual contributor role with architectural influence. You will help define SI budgets and design constraints, not simply verify completed layouts, and will work closely with package, PCB, PHY, memory and system teams.

Location: Barcelona, Spain, Hybrid
Level: Senior

Responsibilities

• Own signal integrity from silicon package through board and system channel

• Define loss, crosstalk and jitter budgets

• Perform pre layout feasibility studies

• Guide routing, stackup and layer assignment

• Run 3D EM extraction of package and board structures

• Perform statistical and time domain channel simulation

• Own PCIe Gen6 channel design and compliance margining

• Support LPDDR interface timing and bus level closure

• Define model quality requirements for passivity, causality and DC accuracy

• Set SI requirements for package, OSAT and component vendors

• Coordinate models with PHY, DRAM and package suppliers

• Correlate simulations with VNA, TDR and silicon measurements

• Support board bring up and SI debug

• Automate analysis and post processing with Python

Requirements

• 8+ years of signal integrity experience

• Background in high speed digital systems

• Strong package level SI experience

• 3D EM extraction experience

• HFSS, SIwave, Clarity, Sigrity, Keysight or equivalent

• Proven SerDes channel closure experience

• PCIe Gen5, Gen6 or comparable interface experience

• DDR5, LPDDR5, LPDDR6 or HBM experience

• Strong IBIS and IBIS AMI knowledge

• Channel simulation experience

• Ability to analyse substrate stackups and bump maps

• Strong understanding of loss, crosstalk, jitter and channel behaviour

• Python scripting for automation and analysis

Optional / Desired

• 2.5D, interposer or chiplet package design

• Advanced substrate experience

• Material characterisation

• Measurement and simulation correlation

• OCP rack platform experience

• High speed connector and backplane experience

• PyAEDT

• scikit rf

• Automated engineering workflows

What's in it for you?

• Flexible working hours

• Hybrid model, 4 days office, 1 day from home

• 1 week per year working from anywhere

• 25 days annual leave plus December 24 and 31

• Monthly food allowance

• Private medical insurance

• Relocation bonus

• Housing search support

• Visa support if required

• Family relocation support

• Virtual shares

• Language classes

• Tax incentive, subject to eligibility