Staff Engineer, Physical Design - València

Analog Devices; Valencia; Presencial; EUR 90.000 - 120.000; Jornada completa

Descripción de la vacante

Analog Devices in Valencia, Spain, is seeking an experienced senior digital implementation engineer to own and deliver large digital subsystems. You will drive floorplanning, place-and-route, and timing closure within a cross-functional team, ensuring tape-out readiness for 40nm processes.

The role requires deep knowledge of CTS/STA, ECO methodologies, LVS/DRC, and Cadence tooling, with scripting in Tcl, SKILL, and Perl.

Formación

• B.Tech/M.Tech in EE/ECE with 10+ years of digital implementation experience.
• Strong floorplanning, place-and-route, CTS, STA, ECO methodology.
• Tape-out ready 40nm digital implementation experience.
• Scripting in Tcl, SKILL and Perl; Cadence tools experience.
• Knowledge of CPF/UPF methodology is a plus.

Responsabilidades

• Floorplan development including power/ground and clock distribution.
• Logic synthesis, cell placement, and interconnect routing.
• Equivalence-checking, timing closure, and physical verification (LVS, DRC).
• Collaborate with RTL designers to resolve challenging problems.
• Own and deliver digital subsystems of significant size and complexity.
• Develop schedules and monitor progress; coordinate across geographies.

Conocimientos

floorplanning

place and route

CTS

STA

ECO methodology

power analysis

physical design verification

40nm digital implementation

scripting

Cadence tools

versioning tools

CPF/UPF knowledge

GDS2 knowledge

ownership

teamwork

communication

Educación

B.Tech/M.Tech in EE/ECE

Herramientas

Cadence tools

Perforce/Methodics

GDS2 database

Descripción del empleo

In this role you will deliver digital subsystems and high-precision analog blocks for next‑gen consumer products. You’ll work within a cross‑functional CSS team focused on capacitive sensing and optical sensing, shaping devices used in portable electronics. You’ll apply state‑of‑the‑art physical design methods to enable scalable, tape‑out ready designs and collaborate across geographies to meet schedule milestones. This is a growth‑oriented position at a global leader driving intelligent edge solutions.

• Floorplan development including power/ground and clock distribution
• Logic synthesis, cell placement, and interconnect routing
• Equivalence-checking, timing closure, and physical verification (LVS, DRC)
• Collaborate with RTL designers to resolve challenging problems
• Own and deliver digital subsystems of significant size and complexity
• Develop schedules and monitor progress
• Coordinate effective teamwork across geographically dispersed locations
• B.Tech/M.Tech in EE/ECE with 10+ years of digital implementation experience
• Strong knowledge of floor planning, place and route, CTS, STA, ECO methodology, power analysis, and physical design verification
• Broad experience in synthesis and timing constraints
• Experience with 40nm digital implementation
• Scripting skills in Tcl, SKILL, and Perl
• Cadence tool experience preferred
• Experience with Perforce/Methodics for versioning
• Knowledge of CPF/UPF methodology (advantage)
• Cadence Virtuoso knowledge (advantage)
• Tape-out ready GDS2 database experience (advantage)
• Technical ownership and hands-on implementation capability
• Strong interpersonal, teamwork and communication skills
• teamwork
• communication
• ownership
• floorplanning
• place and route