Senior Physical Design Engineer

Mpowering People; München; Vor Ort; EUR 70.000 - 90.000; Vollzeit

Zusammenfassung

A prominent technology firm in Munich is seeking an experienced Senior Physical Design Engineer to join their VLSI R&D team. In this role, you'll own the implementation flow and collaborate on cutting-edge silicon designs. The ideal candidate has over 8 years of physical design experience, a strong background in advanced nodes, and proficiency in scripting. This full-time position offers a chance to work on innovative projects within a supportive team environment.

Qualifikationen

• 8+ years of experience in Physical Design.
• Strong background with advanced process nodes (5nm and below preferred).
• Proficiency in scripting necessary for automation.

Aufgaben

• Act as block/IP owner from RTL to GDSII, ensuring horizontal domain coverage.
• Collaborate with architecture and front-end design teams to improve QoR.
• Mentor and support other engineers, sharing expertise.

Kenntnisse

Physical Design

RTL to GDSII flow

Synthesis and DFT insertion

Scripting (Tcl, Python, Perl, TCSH)

High-speed interfaces (DDR/PCIe)

Ausbildung

BSc or MSc in Electrical or Computer Engineering

Jobbeschreibung

Overview

Be among the first 25 applicants. Direct message the job poster from Mpowering People. Do you want to work on cutting-edge silicon for next-generation systems? I am looking for an experienced Senior Physical Design Engineer to join an automotive tier 1's VLSI R&D team in Munich, Germany.

About the Role

The Physical Design team works in a startup-like environment within a global technology leader. Each engineer has true end-to-end ownership — from definition and execution through to full sign-off. You’ll collaborate closely with design and architecture teams, driving methodologies, solving convergence challenges, and delivering silicon from concept to tape-out.

In this role, you’ll also be part of the Technology Methodology & Execution team, developing methodologies and flows for multiple product lines and executing complex subsystems/IPs for our next-generation imaging radar SoCs. This is a chance to work hands-on with advanced nodes and high-speed interfaces while shaping the design process itself.

Key Responsibilities

• Act as block/IP owner from RTL to GDSII, ensuring horizontal domain coverage.
• Collaborate with architecture and front-end design teams to improve QoR, convergence, and design methodologies.
• Own the full implementation flow: Synthesis, DFT insertion, Floorplanning, Place & Route, and sign-off.
• Sign-off across STA, IR/EM, Physical Verification, Logic Equivalence Checking, and Low Power Verification.
• Explore and deploy new methodologies to enhance PPA and turnaround time.
• Evaluate emerging tools, technologies, and features to bring measurable innovation and ROI.
• Mentor and support other engineers, sharing expertise and driving team excellence.

Qualifications

• BSc or MSc in Electrical or Computer Engineering.
• 8+ years of experience in Physical Design.
• Strong background with advanced process nodes (5nm and below preferred).
• Familiarity with high-speed interfaces such as DDR/PCIe (a plus).
• Experience building or maintaining implementation flows and tools.
• Proficiency in scripting (Tcl, Python, Perl, TCSH).
• Strong team player with excellent communication skills and a proactive mindset.

Seniorit y level

• Mid-Senior level

Employment type

• Full-time

Job function

• Engineering and Design
• Industries: Automation Machinery Manufacturing

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