Staff Engineer Functional Verification & Methodology (f/m/div)

Infineon Technologies AG; München; Vor Ort; EUR 60.000 - 80.000; Vollzeit

Zusammenfassung

Infineon Technologies AG is looking for a Staff Engineer Functional Verification & Methodology to join our Research & Development team in Munich. You will drive verification projects, create verification plans, and develop test scenarios using UVM and System Verilog.

The ideal candidate will have a university degree in Electrical Engineering or Computer Science, with at least 3 years of relevant experience. Familiarity with microcontroller-based ICs and strong communication skills in English are critical for success.

Qualifikationen

• At least 3 years of experience in Metric Driven Verification (digital and mixed signal).
• Experience working with microcontroller-based ICs and with security and safety requirements.
• Excellent communication skills in English; German is a bonus.

Aufgaben

• Create and define verification plans.
• Develop the verification environment for our ICs using Universal Verification Methodology (UVM).
• Implement test scenarios using System Verilog and verify functionality with constrained-random approach.
• Develop assertions in System Verilog for formal verification.
• Interact with other disciplines to define verification plans and strategies.
• Enhance our pool of state-of-the-art verification methods.
• Provide proactive support to internal stakeholders.

Kenntnisse

Metric Driven Verification

Universal Verification Methodology (UVM)

System Verilog

Technical leadership

Communication skills

Ausbildung

University degree in Electrical Engineering, Computer Science or similar

Tools

Microcontroller-based ICs

RTL design

Firmware

Jobbeschreibung

As a Staff Engineer Functional Verification & Methodology on our Research & Development team, you will shape the future of technology by driving projects and bringing ideas to life.

Key responsibilities

• Create and define verification plans
• Develop the verification environment for our ICs using Universal Verification Methodology (UVM)
• Implement test scenarios using System Verilog and verify functionality with constrained-random approach
• Develop assertions in System Verilog for formal verification
• Interact with other disciplines—Concept and Application Engineering—to define verification plans and strategies
• Enhance our pool of state‑of‑the‑art verification methods
• Provide proactive support to internal stakeholders of our verification flow environment

Qualifications

• University degree in Electrical Engineering, Computer Science or similar
• At least 3 years of experience in Metric Driven Verification (digital and mixed signal)
• Experience working with microcontroller‑based ICs and with security and safety requirements
• Excellent know‑how with UVM, especially using System Verilog
• Experience in technical leadership (plus)
• Knowledge in RTL design and firmware
• Excellent communication skills in English; German is a bonus

We embrace diversity and inclusion and welcome everyone for who they are. We are an equal‑opportunity employer and are committed to give all applicants and employees equal opportunities.