Senior Engineer Digital IP (f/m/div)

Infineon Technologies AG; Dresden; On-site; EUR 90,000 - 120,000; Full time

Job summary

Infineon Technologies AG in Dresden is seeking a Senior Engineer Digital IP to shape the future of its semiconductor IP portfolio. You will implement RTL in SystemVerilog/Verilog, document designs, and support integration and release readiness across digital IP blocks.

You will drive quality by applying lint, CDC, RDC, synthesis, and ATPG checks, debug complex issues with verification and architecture teams, and contribute to IP development for interfaces like I2C, UART, SPI and AHB/APB.

Qualifications

• Bachelor’s or Master’s degree in electrical engineering, electronics engineering, computer engineering, or a related field.
• 3+ years of experience in semiconductor digital IP design and RTL development with hands-on execution.
• Proven expertise in RTL coding, design documentation, release execution, and IP integration support.
• Strong proficiency in SystemVerilog and Verilog.
• Knowledge of bus protocols such as AHB/APB is a plus.
• Experience with Lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related design quality flows.
• Experience with automated, configurable, or generator-based RTL development flows for IP creation and release.
• Interest in applying AI-assisted engineering tools to RTL development and release readiness.
• Working knowledge of UNIX and Windows environments and version control systems like Git or Perforce.

Responsibilities

• Hands-on digital IP design execution, RTL implementation, documentation, integration support, and release readiness.
• Develop high-quality RTL in SystemVerilog/Verilog for reusable IP blocks.
• Drive design quality closure through Lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and sign-off activities.
• Debug and resolve block-, integration-, and system-level issues with Verification and Architecture teams.
• Support development and integration of IPs such as I2C, UART, SPI, and AHB/APB interfaces.
• Work with automated RTL development flows to improve reuse, scalability, consistency, and productivity.
• Establish and follow robust design processes and release practices to minimize bugs in IP qualification.

Skills

RTL development

SystemVerilog

Verilog

IP design

Release execution

Collaboration

AI-assisted tools

Unix/Linux knowledge

Windows knowledge

Education

Bachelor or Master in Electrical/ Electronics/ Computer Engineering

Tools

Git

Perforce

Job description

#WeAreIn for jobs that impact everyone's life. Join the thinkers, builders, and problem- solvers behind tomorrow’s technology. As a Senior Engineer Digital IP in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?

Your role Key responsibilities in your new role

• Hands-on digital IP design execution, RTL implementation, design documentation, integration support, and release readiness.
• Develop high-quality RTL in System Verilog/Verilog for reusable, configurable, and integration-ready IP blocks.
• Drive design quality closure through Lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related sign-off activities.
• Debug and resolve block-level, integration-level, and system-level design issues in close collaboration with Verification and Architecture.
• Support development and integration of communication and peripheral IPs such as I2C, UART, SPI, AHB/APB-based interfaces, and similar digital IP blocks.
• Work with automated, configurable, and generator-based RTL development flows to improve reuse, scalability, consistency, and design productivity.
• Establish and follow robust design processes, quality gates, and release practices to minimize bug escapes from the IP qualification flow.

This position is limited to 21 months

Your profile Qualifications and skills to help you succeed

• Bachelor’s or master’s degree in electrical engineering, Electronics Engineering, Computer Engineering, or a related field.
• 3+ years of experience in semiconductor digital IP design and RTL development, with strong hands‑on execution.
• Proven expertise RTL coding, design documentation, RTL release execution, and integration support.
• Strong proficiency in System Verilog and Verilog.
• Knowledge of commonly used bus protocols such as AHB/APB is a plus.
• Practical experience with Lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related design quality flows.
• Experience with automated, configurable, or generator-based RTL development flows for IP creation, integration, and release preparation.
• Strong interest in applying AI-assisted engineering tools to improve RTL development, integration, debug, documentation, automation, quality closure, and release readiness.
• Working knowledge of UNIX and Windows environments, MS Office tools, and version control systems such as Git or Perforce.
• Proactive and collaborative approach to risk identification, issue resolution, and stakeholder communication.

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Are you in?

We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.

Please let your recruiter know if you need any accommodations during the interview process.

Learn more about our various contact channels and about Diversity & Inclusion at Infineon.

Felix Krackau