Senior Staff Engineer Digital IP (f/m/div)

Infineon Technologies AG; Dresden; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

Infineon Technologies AG is seeking an experienced semiconductor digital IP design engineer to own the full design lifecycle for digital IP blocks. You will develop high-quality SystemVerilog/Verilog RTL for industry interfaces and contribute to automation and RTL flow improvements.

With 8+ years of hands-on experience, you will collaborate across Verification, Architecture, Physical Design, DFX, Firmware, and System teams, mentoring engineers and expanding ownership toward broader IP

Qualifikationen

• Bachelor’s or Master’s degree in Electrical, Electronics, Computer Engineering, or a related field.
• 8+ years of hands-on semiconductor digital IP design and RTL development experience.
• Strong expertise in micro-architecture, SystemVerilog/Verilog RTL coding, design documentation, integration support, and RTL release execution.
• Experience with automated, configurable, or generator-based RTL development flows, including release containers, configuration control, version control, and traceability.
• Scripting or software development experience, especially Python, for automation, code generation, tooling, configuration management, or flow improvement.
• Practical experience or strong interest in AI-assisted engineering for RTL development, code review, regression analysis, log triage, documentation, checklist automation, quality closure, and release readiness.
• Working knowledge of UNIX/Windows environments, MS Office tools, and version control systems such as Git or Perforce.

Aufgaben

• Shape digital IP solutions by owning the full design lifecycle from micro-architecture to IP release.
• Develop high-quality, reusable IP blocks in SystemVerilog/Verilog for I2C, UART, SPI, and AHB/APB interfaces with configurable RTL flows.
• Apply AI-assisted engineering methods to accelerate development, improve debug efficiency, and optimize release readiness.
• Collaborate with Verification, Architecture, Physical Design, DFX, Firmware, and System teams to solve complex design challenges.
• Mentor engineers, guide design reviews and methodologies, influence architectural decisions, and expand ownership toward broader IP and architecture responsibilities.

Kenntnisse

RTL development

SystemVerilog/Verilog

AI-assisted engineering

Python scripting

Automation tooling

Code review

Version control (Git/Perforce)

Ausbildung

Bachelor/Master in Electrical/Electronics/CE

Tools

Git

Perforce

Jobbeschreibung

Your Role

Key responsibilities in your new role

• Shape digital IP solutions by owning the full design lifecycle— from micro-architecture and RTL development to integration, quality sign‑off, and successful IP release.
• Develop high‑quality, reusable IP blocks in SystemVerilog/Verilog, working on industry‑relevant interfaces such as I2C, UART, SPI, and AHB/APB while leveraging advanced automation and configurable RTL flows.
• Drive technical excellence and innovation by applying AI‑assisted engineering methods to accelerate development, improve debug efficiency, enhance quality, and optimize release readiness.
• Collaborate with cross‑functional experts across Verification, Architecture, Physical Design, DFX, Firmware, and System teams to solve complex design challenges.
• Grow your leadership impact by mentoring engineers, guiding design reviews and methodologies, influencing architectural decisions, and expanding your ownership toward broader IP and architecture responsibilities.

Your Profile

Qualifications and skills to help you succeed

• Bachelor’s or Master’s degree in Electrical, Electronics, Computer Engineering, or a related field.
• 8+ years of hands‑on semiconductor digital IP design and RTL development experience.
• Strong expertise in micro‑architecture, SystemVerilog/Verilog RTL coding, design documentation, integration support, and RTL release execution.
• Experience with automated, configurable, or generator‑based RTL development flows, including release containers, configuration control, version control, and traceability.
• Scripting or software development experience, especially Python, for automation, code generation, tooling, configuration management, or flow improvement.
• Practical experience or strong interest in AI‑assisted engineering for RTL development, code review, regression analysis, log triage, documentation, checklist automation, quality closure, and release readiness.
• Working knowledge of UNIX/Windows environments, MS Office tools, and version control systems such as Git or Perforce.

Contact: Felix Krackau

We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities.

We base our recruiting decisions on the applicant’s experience and skills. Learn more about our various contact channels. We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.

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