Senior Digital ASIC Design Engineer Synthesis (m/f/d)

advantestcareers; Böblingen; Vor Ort; EUR 70.000 - 110.000; Vollzeit

Zusammenfassung

Advantest is seeking a Digital ASIC Design Engineer to drive architecture development for CMOS designs and RTL coding of digital modules. You will verify at module and chip levels, generate test plans, and document functionality.

Collaboration with system architects and partners will be essential as you optimize timing and power across IP blocks and the chip top level. The role involves supporting floor-planning and physical design, with close teamwork to deliver high-quality results on schedule

Qualifikationen

• Background in digital design (SOC) and silicon development cycle.
• Experience in RTL coding (Verilog and SystemVerilog) is required.
• Experience with standard simulation tools for digital designs.
• Unix/Linux environment familiarity and programming basics.

Aufgaben

• Architecture development for CMOS designs.
• Design and RTL coding of digital modules.
• Verification on module and chip level including test plans.
• Documentation of implemented functionality.
• Constraint generation and synthesis of IP blocks and chip top level.
• Analysis of timing and power consumption.
• Support for floor-planning and physical design.
• Close collaboration with design partners.

Kenntnisse

RTL coding (Verilog/SystemVerilog)

Digital design (SOC)

ASIC design methodologies

Unix/Linux

English language skills

Ausbildung

University degree, Diploma or BS EE

Tools

Standard digital simulators

Jobbeschreibung

Join a global, highly skilled engineering team at the heart of Advantest’s cutting edge IC test solutions. As a Digital ASIC Design Engineer, you will help create the key technologies that enable the next generation of semiconductor testing. You will work on complex mixed signal ASICs used in Advantest’s industry leading testers, taking digital modules and subsystems from first concept all the way to silicon in the final system, giving you true end to end ownership. In this role, you will collaborate closely with system architects and design engineers. You will generate constraints for synthesis of IP blocks and the chip top level integration. You will analyze critical paths for robust designs, keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale.

Job Duties & Responsibilities

• Architecture development for CMOS designs
• Design and RTL coding of digital and full-custom modules
• Verification on module and chip level including test plan/cases generation.
• Documentation of implemented functionality
• Constraint generation and synthesis of IP blocks and the chip top level
• Analysis of timing and power consumption
• Support for floor-planning and physical design
• Close collaboration with design partners

Qualifications

• University degree, Diploma or BS EE
• Background in digital design (SOC), Application Specific Integrated Circuit (ASIC) design methodologies and silicon development cycle
• Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog)
• Experience with standard simulation tools for digital designs
• Basic knowledge about UNIX* or Linux* environment and using programming languages
• Technical communication, team work and problem solving skills
• English language skills