DFT Engineer

Intellectual Capital Resources Ltd; Nordrhein-Westfalen; Vor Ort; EUR 117.000 - 170.000; Vollzeit

Zusammenfassung

Intellectual Capital Resources Ltd seeks a seasoned DFT Engineer to join a cutting-edge semiconductor team focused on high-speed chip-to-chip connectivity. The role spans DFT implementation, test pattern development, timing, simulation, and silicon bring-up across complex ASIC/SoC designs.

The successful candidate will contribute to IJTAG-based methodologies, hierarchical MBIST and ATPG across multiple fault models, along with scripting to automate DFT flows and improve overall efficiency.

Qualifikationen

• Bachelor's degree or higher in Electronics, Electrical Engineering, Computer Engineering or a related discipline.
• 5+ years of experience in DFT.
• Experience with IJTAG methodologies and DFT technologies.

Aufgaben

• Hierarchical MBIST and scan insertion, including scan compression.
• Boundary Scan Design (BSD) implementation.
• ATPG pattern generation, coverage analysis and driving towards high coverage metrics.
• Running and debugging pattern simulations with timing.
• Defining test-mode timing constraints and analysing timing reports.
• Supporting timing convergence across test modes.
• Developing cycle-accurate functional patterns using IJTAG methodologies.
• Working with test and production engineering during probe and final test.
• Supporting device bring-up and debugging silicon issues.
• Developing scripts and automation to improve DFT flows.

Kenntnisse

DFT expertise

IJTAG

MBIST insertion

ATPG patterns

Scripting

SystemVerilog

Timing-aware simulation

Ausbildung

Bachelor's degree in Electronics or related

Tools

EDA tools

Jobbeschreibung

DFT Engineer

Lausanne, Switzerland or UK

I’m working with an innovative semiconductor company developing high-speed, energy-efficient chip-to-chip connectivity solutions for next-generation electronic systems.

They are looking for an experienced DFT Engineer to join their growing engineering team, working across DFT implementation, test pattern development, timing, simulation and silicon bring-up.

This would suit someone who enjoys being hands-on technically and wants to work on complex designs within a fast-moving semiconductor environment.

Key Responsibilities

• Hierarchical MBIST and scan insertion, including scan compression
• Boundary Scan Design (BSD) implementation
• ATPG pattern generation, coverage analysis and driving towards high coverage metrics
• Running and debugging pattern simulations with timing
• Defining test-mode timing constraints and analysing timing reports
• Supporting timing convergence across test modes
• Developing cycle-accurate functional patterns using IJTAG methodologies
• Working closely with test and production engineering teams during probe and final test
• Supporting device bring-up and debugging silicon issues
• Developing scripts and automation to improve DFT flows

What We’re Looking For

• 5+ years of experience in DFT
• Experience across DFT implementation, test pattern development and simulation
• Experience contributing to DFT solutions for complex ASIC or SoC designs
• Strong knowledge of IJTAG methodologies
• Experience with hierarchical MBIST insertion
• Experience with hierarchical scan insertion and scan compression
• Strong ATPG experience across different fault models
• Experience analysing fault coverage and driving coverage closure
• Strong debugging skills, particularly around timing-aware pattern simulation
• Experience with industry-standard EDA tools for DFT, timing and simulation
• Good scripting skills for automation
• Knowledge of SystemVerilog

Education

Bachelor’s degree or higher in Electronics, Electrical Engineering, Computer Engineering or a related discipline.

The Opportunity

You’ll be joining a company working at the forefront of high-speed semiconductor connectivity, with the opportunity to contribute across the complete DFT lifecycle, from implementation and pattern generation through to silicon bring-up and production test.

The role can be based in Lausanne, Switzerland or the UK.