Advanced R&D - Physical Design Engineer

Kandou Ai; Deutschland; Vor Ort; EUR 127.000 - 180.000; Vollzeit

Zusammenfassung

Kandou is seeking an Experienced Advanced R&D - Physical Design Engineer in Lausanne to translate high-speed IP into physical layouts for FinFET nodes, bridging logic and physical design, and achieving Power, Performance, and Area targets.

You will own synthesis, floorplanning, CTS, routing, SDC constraints, and collaborate with digital designers to resolve bottlenecks, delivering sign-off packages for tape-out.

Qualifikationen

• 5+ years of physical design experience focusing on synthesis, SDC, CTS and place-and-run.
• Experience with deep-submicron FinFET processes and low-power techniques (UPF).
• Proven tape-out experience on leading-edge nodes (7nm/5nm/3nm).

Aufgaben

• Own block synthesis, floorplanning, placement, CTS, and routing.
• Develop SDC constraints and ensure design intent aligns with physical realization.
• Collaborate with digital design to fix P&R bottlenecks and optimize timing.
• Prepare sign-off packages and tape-out documentation.

Kenntnisse

Scripting (Tcl, Python)

Flow automation

Timing analysis

Team collaboration

Ausbildung

Masters or Ph.D. in E.E. or Communications

Tools

Cadence Genus/Innovus/Tempus

Synopsys Design Compiler/ICC2/PrimeTime

Calibre

Jobbeschreibung

At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems - a critical barrier to scalable adoption.Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient . Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency - unlocking unprecedented efficiency for AI training and inference at scale.

Job title: Advanced R&D - Physical Design Engineer

Location : Lausanne, Switzerland

The Physical Design (PD) Engineer translates high-speed communication IP digital designs into physical GDSII layouts for advanced FinFET nodes. You will bridge logic design, owning block-to-chip implementation from netlist to final physical sign-off, ensuring PPA (Power, Performance, and Area) targets are met.

Immediate key objective

• Drive block-level physical implementation-covering synthesis, SDC constraints, floorplanning, placement, CTS, and routing-meeting strict frequency, area, and power targets.
• Execute timing closure across multiple corners and modes (MCMM) utilizing static timing analysis (STA) and generating targeted ECOs.
• Drive full physical verification closure sign-off in deep-submicron FinFET technologies.

Responsibility

• Own block synthesis, floorplanning, placement optimization, CTS, and routing.
• Develop and refine SDC constraints to ensure design intent matches physical realization.
• Collaborate with the digital design team to resolve logic or architectural bottlenecks affecting P&R convergence.
• Generate progress reports, document implementation flows, and prepare sign-off packages for tape-out.

Required Experience

• 5+ years of hands-on physical design experience focusing on synthesis, SDC constraints, CTS, and place and route for high-speed systems.
• Strong technical background in deep-submicron CMOS/FinFET physical effects, crosstalk, and high-frequency clock network design.
• Proven experience of taking complex blocks from netlist through successful physical implementation.
• Direct experience with advanced low-power implementation techniques (UPF, power gating).
• Proven tape-out experience in advanced FinFET nodes (e.g., 7nm, 5nm, or 3nm).
• Experience handling complex block-to-chip hierarchical assembly, pin placement, and top-level routing constraints..

Required Skills

• Expert proficiency with industry-standard implementation and sign-off tools (e.g., Cadence Genus/Innovus/Tempus or Synopsys Design Compiler/ICC2/PrimeTime, and Calibre).
• Deep understanding of SDC creation, and MCMM timing management.
• Strong scripting skills (Tcl, Python) for flow automation and design data analysis.
• Analytical mindset to debug congestion routing issues, and complex timing violations.
• Self-motivated with strong sense of ownership; effective communicator and team player.

Required Education

• Masters or Ph.D. in E.E., Communications or other relevant fields

https://kandou.ai/