Lead Standard Cells Characterization Engineer

Cisco Systems, Inc; Capital; On-site; COP 120,000,000 - 180,000,000; Full time

Job summary

Cisco Systems, Inc. is seeking an experienced characterisation engineer to lead end-to-end flows for standard cell libraries. You will define methodologies, automate timing and power analyses, and drive correlations across multiple tools and foundry flows.

The role requires deep knowledge of Liberty formats, parasitic extraction, and RC corner alignment, plus strong scripting skills in Tcl, Perl, or Python to enable repeatable, scalable characterization across library releases.

Qualifications

• Bachelor's degree with 6+ years of relevant experience.
• Experience characterizing standard cell libraries with PrimeLib, Liberate, or equivalent tools.
• Strong understanding of Liberty formats (NLDM, CCS) and TSMC / foundry characterization flows.
• Experience with parasitic extraction (StarRC), LVS, and RC corner alignment.
• Solid understanding of CMOS device behavior, timing arcs, and power modeling in deep-submicron nodes.

Responsibilities

• Lead end-to-end characterization flow for standard cell libraries from extracted netlists to Liberty delivery.
• Define and maintain characterization methodology, templates, and automation for timing, power, noise, leakage.
• Drive correlation closure for delay, transition, capacitance, and leakage.
• Own extraction-to-char integration: LVS/StarRC setup, RC corner alignment, and netlist quality gates.
• Debug characterization failures at netlist, simulation, and Liberty-model levels; root-cause analysis.

Education

Bachelor's degree in Electrical Engineering, Computer Science, or related field

Master's degree (preferred) / PhD (optional) with related experience

CMOS device understanding

Timing/Power modeling knowledge

Tools

PrimeLib

Liberate

StarRC

LVS

RC corner / PVT flows

Netlist extraction / CCM tools

Job description

Cisco Systems, Inc. is seeking an experienced characterisation engineer to lead end-to-end flows for standard cell libraries. You will define methodologies, automate timing and power analyses, and drive correlations across multiple tools and foundry flows.

The role requires deep knowledge of Liberty formats, parasitic extraction, and RC corner alignment, plus strong scripting skills in Tcl, Perl, or Python to enable repeatable, scalable characterization across library releases.