Digital Design & Verification (RTL + UVM + Microarchitecture)

Botic Partners; Zürich; On-site; CHF 100,000 - 130,000; Full time

Job summary

Botic Partners is looking for Senior Digital Engineers in Zürich to join a deep-tech compute architecture team. The role involves developing RTL for compute subsystems and contributing to microarchitecture definition.

Candidates should have a strong background in RTL coding and UVM methodologies. This role combines RTL development with verification environments, making it essential for applicants to collaborate across technical teams.

Qualifications

• Strong background in RTL coding (SystemVerilog/Verilog).
• Solid experience with UVM and modern DV methodologies.
• Knowledge of SoC integration, buses, protocols (AXI/APB).

Responsibilities

• Develop RTL for compute subsystems, controllers, datapaths and interfaces.
• Contribute to microarchitecture definition and technical reviews.
• Build UVM-based verification environments and test plans.

Skills

RTL coding (SystemVerilog/Verilog)

UVM and modern DV methodologies

Knowledge of SoC integration

Exposure to FPGA and verification

Job description

Digital Design & Verification (RTL + UVM + Microarchitecture)

We are searching for Senior Digital Engineers with strong RTL and Verification expertise to join a deep-tech compute architecture team. The role involves hybrid responsibilities across microarchitecture, RTL development, DV environments and subsystem integration.

Responsibilities

• Develop RTL for compute subsystems, controllers, datapaths and interfaces
• Contribute to microarchitecture definition and technical reviews
• Build UVM-based verification environments and test plans
• Drive functional coverage, constrained-random testing and debug
• Support FPGA bring-up and silicon validation activities
• Collaborate with physical design, architecture and mixed-signal teams

Requirements

• Strong background in RTL coding (SystemVerilog/Verilog)
• Solid experience with UVM and modern DV methodologies
• Knowledge of SoC integration, buses, protocols (AXI/APB)
• Exposure to FPGA, DFT, CDC/RDC, linting and subsystem verification
• Ability to work across design + verification flows with technical ownership