Lead Custom Design Engineer

Ignite Next GmbH; Zürich; Hybrid; CHF 180.000 - 240.000; Vollzeit

Zusammenfassung

Ignite Next GmbH in Zürich, Switzerland invites a senior hardware architect to lead development of compute-in-memory SRAM (ComputeRAM). You will own architecture, circuit design, verification, and silicon correlation for 5 nm and below, and manage a small team of custom designers and layout engineers.

The role focuses on bitcell-adjacent periphery, datapath interfaces, data movement optimization, and close collaboration with layout, digital, backend, DFT, and test to deliver production-grade

Qualifikationen

• 7+ years in custom digital, memory, or analog design.
• End-to-end ownership of production-grade functional blocks, including sign-off and silicon correlation.
• Strong collaboration with layout, digital, backend, DFT and test teams.
• Experience with high-performance, low-power design on advanced nodes (FinFET, 5 nm+).

Aufgaben

• Own the product roadmap: define specs, PPA targets, verification depth, and quality bars for new SRAM variants and adjacent blocks.
• Design and verify memory or datapath subsystems (sense amps, data drivers, multipliers, adders, register files, timing/control FSMs).
• Architect for advanced nodes: manage variation, stability, noise, wake-up and low-power behavior.
• Define clean digital boundaries and timing budgets for integration into mixed-signal flows.
• Plan bring-up, build characterization benches, analyze ATE data, publish correlation/errata with fixes.
• Specify and validate redundancy/repair schemes; coordinate with MBIST/Scan test coverage.
• Collaborate with layout on floorplans, matching, shielding, routing; address EM/IR early.
• Mentor designers, run reviews, enforce checklists, and grow automation (Python/Tcl).

Kenntnisse

Team leadership

Memory design

Digital design

Verification

Python scripting

Ausbildung

MS or PhD in Electrical/Computer Engineering

Tools

Python

Tcl

DFT tools

Jobbeschreibung

Zürich, Switzerland
Seniority: 7+ years (custom digital, analog, or memory), team leadership

Lead the development of high-performance, custom based digital compute or SRAM memory designs to power our compute-in-memory SRAM (ComputeRAM®). You will own architecture, circuit design, verification, and silicon correlation for advanced nodes down to 5 nm and below, and you will lead a small team of custom designers and layout engineers to predictable, production-grade outcomes. Expect hands-on work on bitcell-adjacent periphery, datapath interfaces, optimizing data movement, as well as tight collaboration with full-custom layout, digital, backend, DFT, and test.

What you’ll do

• Own the product roadmap: define specs, PPA targets, verification depth, and quality bars for new SRAM variants and CxR-adjacent custom blocks.
• Design & verify memory or datapath subsystems, including sense amps, data drivers, multipliers, adders, register files, timing/control FSMs, etc..
• Engineer for advanced nodes: close on variation (corners, Monte-Carlo), stability, noise/IR drop, device reliability, and wake-up/low-power behaviors in FinFET and FDSOI.
• Integrate for product: define clean digital boundaries (standard-cell and bus interfaces), latency/handshake contracts, and timing budgets so blocks drop into a digital-on-top mixed-signal flow.
• Silicon correlation: plan bring-up, build characterization benches, analyze ATE data, and publish correlation and errata with clear fixes.
• Redundancy & test: specify and validate redundancy/repair schemes; work with DFT (MBIST and Scan) test coverage; sign off on a production test plan.
• Partner with layout: co-plan floorplans, matching/guarding, shielding, and routing topologies; review extraction and fix EM/IR issues early.
• Elevate method & team: coach designers, run reviews, enforce checklists, and grow automation (Python/Tcl) for regressions, reporting, and collateral generation.

Outcomes (first 18 months)

• Tape-in and silicon of at least one production-grade CxR custom memory block meeting spec across PVT, with signed correlation and test reports.
  
• A reusable design kit (models, constraints, verification plans, char scripts, checklists) that shortens the following variant’s cycle time.
• A high-functioning custom team with clear ownership (periphery, timing/control, modeling, characterization) and reliable delivery metrics.
• Quantified PPA and yield gains from design or methodology improvements you led.

Requirements

• MS or PhD in Electrical/Computer Engineering (or similar) and 7+ years in custom digital, memory, or analog design.
• Track record of end-to-end ownership of production-grade functional blocks, including sign-off and silicon correlation.
• Deep understanding of high-performance and low-power circuit design on FinFET nodes (stability, variation, leakage, performance).
• Experience leading a small team (mentoring, reviews, planning) and coordinating tightly with layout, digital, backend, DFT, and test.
• Clear communication, structured documentation, and a quality-first mindset.
  

Nice to have

• Scripting for design and characterization automation (Python, Tcl) and model/report generation.
• Experience with memory compilers, characterization flows, and verification environments.
• DTCO/STCO exposure to align device, bitcell, and periphery choices with product goals.
• Background with production test strategies.
• Familiarity with compute-in-memory constraints and with integrating custom memory into large digital systems.

Interview flow (indicative)

1. 30-min intro with HR (role/context)
2. First Technical deep dive
3. Second Technical Deep Dive
4. (Optional) Third Technical Deep Dive
5. Systems/product conversation with management