Senior ASIC Engineering Leader—Analog & Mixed-Signal

Cisco Systems; Thalwil; Vor Ort; CHF 180.000 - 240.000; Vollzeit

Zusammenfassung

Cisco Systems seeks an ASIC Engineering Technical Leader in Thalwil, Switzerland to lead high‑speed analog/mixed‑signal ASIC development. You will define, design, and verify subsystems, guiding architecture, verification, and packaging considerations for Cisco platforms.

Collaborate across teams to meet power, performance, and area targets while shaping reusable design methodologies and advanced digital flows.

Qualifikationen

• Masters + 8 years of related experience, or PhD + 5 years of related experience, or equivalent related work experience
• Extensive experience in high-frequency CMOS circuit design and custom analog and mixed-signal circuit design
• Proficiency with the Cadence Virtuoso CAD design environment, including custom layout, DRC, LVS, and parasitic extraction
• Strong programming skills utilizing languages such as Skill, VerilogA, Tcl, Perl, Python, Matlab, or C

Aufgaben

• Define, design, and verify high-performance ASIC subsystems deployed across Cisco platforms
• Oversee the architecture and design of complex analog and mixed-signal circuits
• Collaborate with cross-functional teams to ensure power, performance, and area goals are met
• Guide development of reusable code methodologies, physical design functions, and advanced digital design flows

Kenntnisse

VerilogA

Python

C

Tcl

Perl

Matlab

C

Ausbildung

Masters or PhD in EE or related field

Tools

Cadence Virtuoso

EMX

Momentum

HFSS

Siemens Mentor

Synopsys

Jobbeschreibung

Cisco Systems seeks an ASIC Engineering Technical Leader in Thalwil, Switzerland to lead high‑speed analog/mixed‑signal ASIC development. You will define, design, and verify subsystems, guiding architecture, verification, and packaging considerations for Cisco platforms.

Collaborate across teams to meet power, performance, and area targets while shaping reusable design methodologies and advanced digital flows.