Lead Analog/Mixed-Signal ASIC Architect

Cisco Systems, Inc; Thalwil; Remote; CHF 120,000 - 180,000; Full time

Job summary

Cisco Systems, Inc in Thalwil, Switzerland, seeks an ASIC Engineering Technical Leader to define, design, and verify high-performance analog and mixed-signal subsystems for Cisco's silicon platforms powering AI and cloud infrastructure.

You will oversee architecture and verification strategies, collaborate with cross-functional teams, and guide development of reusable code methodologies and advanced digital flows for high-volume ASIC releases.

Qualifications

• Masters or PhD with related experience.
• Extensive experience in high-frequency CMOS circuit design and analog/mixed-signal design.
• Proficiency with Cadence Virtuoso CAD environment (layout, DRC, LVS).
• Strong programming skills in Skill, VerilogA, Tcl, Perl, Python, Matlab, or C.

Responsibilities

• Define, design and verify high-performance ASIC subsystems.
• Oversee architecture and design of complex analog/mixed-signal circuits.
• Direct verification strategies and reusable coding methodologies for scalable flows.
• Collaborate with cross-functional teams to meet power, performance and area goals.

Skills

CMOS circuit design

Analog & mixed-signal design

Cadence Virtuoso

VerilogA/Tcl/Python

Programming skills

Education

Master's degree

PhD

Tools

Cadence Virtuoso

Siemens/Mentor

Synopsys

EMX

Momentum

HFSS

Job description

Cisco Systems, Inc in Thalwil, Switzerland, seeks an ASIC Engineering Technical Leader to define, design, and verify high-performance analog and mixed-signal subsystems for Cisco's silicon platforms powering AI and cloud infrastructure.

You will oversee architecture and verification strategies, collaborate with cross-functional teams, and guide development of reusable code methodologies and advanced digital flows for high-volume ASIC releases.