Senior AI-Driven SoC Digital Design Engineer

Renesas Electronics Corp.; Zürich; On-site; CHF 120,000 - 180,000; Full time

Job summary

Renesas Electronics Corp. in Zurich invites a senior IC design engineer to lead AI-assisted tool development and integration across the design flow, from requirements to silicon validation.

You will own RTL design, implement Verilog/SystemVerilog, and collaborate with system, analog, verification, firmware, and physical design teams on SoC integration, clock/reset architectures, and low-power techniques. Fluent English required; MSc/PhD preferred.

Qualifications

• Proven hands-on experience developing and integrating AI-based tools into IC design workflows is required.
• Candidates must be able to demonstrate implemented solutions in areas such as requirements engineering, specification generation, RTL design, verification, or design-flow automation.
• MSc or PhD in Electrical Engineering, Microelectronics, Computer Engineering, or a related field.

Responsibilities

• Take technical ownership of internal engineering tools and their existing codebases. Develop enhancements, resolve defects, maintain documentation, manage releases, and provide ongoing support to the engineering team.
• Develop and validate AI-assisted workflows that translate product requirements into specifications for each engineering discipline. Work with domain experts to preserve traceability to source requirements and manage dependencies and requirement changes.
• Build automated tests and review workflows to assess the completeness, consistency, and correctness of generated specifications. Ensure outputs can be checked and approved by the responsible engineers.
• Translate user feedback into tool improvements, maintain integrations with engineering workflows, and evaluate additional AI/LLM applications for requirements analysis, documentation, RTL development, and verification.
• Translate system and product requirements into digital specifications and micro-architectures. Develop RTL in Verilog/SystemVerilog and integrate embedded processors, memories, peripherals, register maps, and on-chip buses into mixed-signal SoCs.
• Own digital design activities including lint, CDC/RDC analysis, synthesis, static timing analysis, and low‑power design. Support physical implementation and timing closure.
• Collaborate with system, analog, verification, firmware, and physical design teams on SoC integration, clock and reset architectures, mixed-signal interfaces, design reviews, and verification planning.
• Support silicon bring-up, laboratory debugging, and product validation through the transition to volume production

Skills

AI tool integration

Verilog/SystemVerilog

RTL design

Embedded processors

Python

Tcl

Software development

Requirement management

English fluency

Cross-functional collaboration

Education

MSc or PhD in Electrical Engineering, Microelectronics, Computer Engineering

Tools

Python

Tcl

EDA toolchains

Job description

Renesas Electronics Corp. in Zurich invites a senior IC design engineer to lead AI-assisted tool development and integration across the design flow, from requirements to silicon validation.

You will own RTL design, implement Verilog/SystemVerilog, and collaborate with system, analog, verification, firmware, and physical design teams on SoC integration, clock/reset architectures, and low-power techniques. Fluent English required; MSc/PhD preferred.