Senior Digital IC Design Engineer - MCU/DSP & Accel IP Lead

onsemi; Marin-Epagnier; On-site; CHF 120,000 - 180,000; Full time

Benefits offered by this job

25 vacation days

Competitive benefits package

International projects

Job summary

onsemi is seeking a Senior Digital IC Design Engineer in Switzerland to lead the development of embedded MCU/DSP systems and accelerator IPs. The role involves architectural definition, verification, and collaboration with software teams to ensure robust integration.

The candidate will drive design methodology improvements, coordinate SDK efforts, and mentor junior engineers in a global, innovative environment with extensive international projects.

Qualifications

• Minimum MS in Electrical Engineering or related field.
• At least 6 years of relevant work experience in semiconductor product development, including engineering leadership.
• Experience with embedded CPUs (e.g. ARM Cortex, RISC-V, DSP), AMBA bus protocols (AHB/APB).
• RTL design of digital IP blocks and systems in Verilog/SystemVerilog.
• Strong technical document writing skills.
• Excellent written and verbal communication skills in English.
• Eligibility to work in Switzerland.

Responsibilities

• Architect, specify, implement, simulate, and benchmark MCU and DSP systems as well as hardware accelerators and peripheral IPs
• Consult the product integration teams in the definition, the integration and use of these systems
• Participate to the verification and FPGA prototyping of these systems
• Coordinate the SDK development with the software team
• Lead project activities
• Contribute to design methodology and design flow improvements.

Skills

Engineering leadership

Project leadership

Written & verbal English

Eligibility to work in Switzerland

English communication

Education

MS in Electrical Engineering

Tools

Verilog

SystemVerilog

ARM Cortex

RISC-V

AMBA (AHB/APB)

Job description

onsemi is seeking a Senior Digital IC Design Engineer in Switzerland to lead the development of embedded MCU/DSP systems and accelerator IPs. The role involves architectural definition, verification, and collaboration with software teams to ensure robust integration.

The candidate will drive design methodology improvements, coordinate SDK efforts, and mentor junior engineers in a global, innovative environment with extensive international projects.