Principal Engineer, Digital Design & RTL Innovation

Infineon Technologies AG; Zürich; Sur place; CHF 140 000 - 190 000; Plein temps

Résumé du poste

Infineon Technologies AG in Zürich invites a Principal Engineer Digital Design to shape future silicon by translating MATLAB algorithms to RTL, evaluating performance, and driving IPs from design to production with cross‑functional teams.

Requires a Master’s or PhD in ECE/CS, 5+ years in ASIC RTL to GDS flow, VHDL and SystemVerilog, DSP design experience, and English fluency. RF/wireless knowledge is a plus, and tape‑out experience is valued.

Qualifications

• Master's or PhD in Electrical Engineering, Computer Science, or related field.
• 5+ years in ASIC RTL to GDS flow; proficiency in VHDL and SystemVerilog RTL.
• Experience in custom digital signal processing design at hardware level, ideally for wireless communications.
• Fluency in English (mandatory)

Responsabilités

• Conceptualize and translate custom complex signal processing algorithms from MATLAB to RTL
• Evaluate performance trade-offs and propose innovative improvements to existing UWB features
• Perform simulations, synthesis, timing and power analysis
• Collaborate closely with cross-functional teams including verification, system, analog, and application engineering with internal and external stakeholders
• Document and share specifications and architectural choices
• Contribute to silicon validation, ensure production release, and drive continuous improvement of existing IPs and design flows
• Mentor and support team members on a day-to-day basis

Connaissances

VHDL

SystemVerilog RTL

ASIC RTL to GDS flow

Digital signal processing

English fluency

Formation

Master's or PhD in Electrical Engineering, Computer Science, or related field

Outils

UPF flow

Synthesis

Timing analysis

Place-and-route

DFT

CDC implementations

Description du poste

Infineon Technologies AG in Zürich invites a Principal Engineer Digital Design to shape future silicon by translating MATLAB algorithms to RTL, evaluating performance, and driving IPs from design to production with cross‑functional teams.

Requires a Master’s or PhD in ECE/CS, 5+ years in ASIC RTL to GDS flow, VHDL and SystemVerilog, DSP design experience, and English fluency. RF/wireless knowledge is a plus, and tape‑out experience is valued.