Physical Design Engineer

IC Resources; Lausanne; Vor Ort; CHF 110.000 - 170.000; Vollzeit

Zusammenfassung

IC Resources in Lausanne is seeking a Physical Design Engineer to help advance next‑generation high‑speed circuits and communications technology. You will participate in the full implementation flow from RTL to GDS in a small, focused R&D team.

The role offers exposure to advanced process nodes, signoff methodologies, and scripting tasks (TCL/Python). Cadence tools experience and SerDes exposure are advantageous for future production silicon path.

Qualifikationen

• Experience across RTL to GDS in digital PD flow.
• Experience with 7nm nodes or below.
• Knowledge of timing closure and STA.
• Familiarity with physical verification and signoff.
• Scripting in TCL/Python/Shell.

Aufgaben

• End-to-end PD from RTL to GDS including signoff.
• Collaborate with R&D to implement new architectures.
• Contribute to methodology improvements and production silicon readiness.

Kenntnisse

Digital PD flow

RTL to GDS

7nm nodes

Timing closure

Scripting TCL/Python

CADENCE tools

SerDes exposure

Tools

Cadence toolset

Jobbeschreibung

This is an exciting opportunity to join small advanced R&D team that is looking to expand. They are looking for a Physical Design Engineer to work on next generation high speed circuit and communications technology.

This is an opportunity to work on advanced semiconductor technology within a highly technical R&D environment, where Physical Design is involved in taking new architectures from development through towards production silicon.

The role would suit a Physical Design Engineer who enjoys working across the full implementation flow and wants exposure to challenging designs at advanced process nodes.

What makes the role interesting:

• Work on advanced semiconductor designs using modern process technologies
• Opportunity to contribute to new architectures rather than simply implementing established designs
• Full RTL to GDS experience across synthesis, place & route and signoff
• Small, technically focused R&D environment with significant scope to influence methodologies and implementation
• Research and development work has a clear route towards future production silicon

The ideal Physical Design Engineer will have:

• Strong experience across the digital Physical Design flow from RTL through to GDS
• Experience working on advanced process nodes, ideally 7nm or below
• Good understanding of modern implementation and signoff methodologies
• Experience with Cadence tools is preferred but not essential
• Experience with timing closure and STA
• Exposure to physical verification and signoff
• Scripting experience, ideally with TCL, Python or Shell
• Experience working with mixed signal or analogue blocks would be a strong advantage
• Experience with SerDes is useful but not essential

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/