SOC Design Engineer

Qualcomm Incorporated; Markham; On-site; CAD 130,000 - 180,000; Full time

Job summary

Qualcomm Canada ULC seeks an experienced ASIC Engineer to define, model, design, verify, implement, and document IP development for high-performance, low-power products. You will work across architecture, RTL design, and cross-functional teams to ensure design convergence and quality.

Responsibilities include developing power control systems on latest nodes, integrating subsystems into SoC, and coordinating with verification, PD, and DFT teams to meet milestones.

Qualifications

• 4+ years ASIC design, verification, validation, integration experience (Bachelor).
• 3+ years with Master's degree in ASIC design/verification.
• 2+ years with PhD in ASIC design/verification.

Responsibilities

• Define and develop next-gen power control IP for ASICs.
• Architect, micro-architect, RTL design across complex projects.
• Collaborate across US/India teams for design convergence and verification.

Skills

RTL coding

Verilog/VHDL/SV

Clock domain crossing

UPF

Bus protocols (AXI/AHB/SPMI/I2C/SPI)

Low power design

Formal verification

Perl/TCL scripting

Post-Si debugging

Spyglass Lint/CDC

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Cadence LEC

Spyglass

0-in

DC-Compiler

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Candidate will be responsible for design/developing next generation power control systems. Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD teams for design convergence. Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC Design and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed. Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.

Skills/Experience Sr Engineer / Staff Engineer 5 to 8 years of strong experience in digital front end design for ASICs Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl, TCL language Expertise in post-Si debug is a plus

Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range and Other Compensation & Benefits:

$129,600.00 - $179,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.