Silicon Validation Architect for High‑Speed Memory

Synopsys, Inc.; Ottawa; On-site; CAD 110,000 - 150,000; Full time

Job summary

Synopsys, Inc. in Ottawa seeks a silicon validation engineer to lead first-silicon bring-up and electrical characterization of high-speed interfaces such as DDR6/LPDDR6/HBM. You will design validation plans, analyze margins, and coordinate across silicon, firmware, and design teams.

You will build automated validation frameworks using Python/C/C++, perform eye diagram analysis, jitter measurements, and VREF optimization, ensuring release-ready silicon and robust test coverage.

Qualifications

• Bachelor's or Master's in Electrical Engineering or related field.
• 3+ years in silicon validation and characterization.
• Proficiency with DDR/LPDDR/HBM protocols and high-speed interfaces.

Responsibilities

• Work on first-silicon bring-up and validation for DDR6, DDR5, LPDDR6/X, LPDDR5/5X, MRDIMM, and HBM test chips.
• Develop and execute validation plans covering functionality, margins, and reliability across corners.
• Perform electrical characterization including eye diagrams, jitter, timing margins, and VREF optimization.
• Drive debug and root-cause analysis of silicon, firmware, board, and test infrastructure issues.
• Build automated validation frameworks and reusable test infrastructure using Python, C/C++, and scripting tools.
• Participate in development of multilayer PCB designs for characterization platforms and customer evaluation kits.
• Generate characterization reports and present silicon performance data to stakeholders.

Skills

Independent problem solving

Cross-functional collaboration

Data analysis & scripting

Education

Bachelor's or Master's in Electrical Engineering

Tools

MATLAB

Python

C/C++

Automated Test Equipment

Job description

Synopsys, Inc. in Ottawa seeks a silicon validation engineer to lead first-silicon bring-up and electrical characterization of high-speed interfaces such as DDR6/LPDDR6/HBM. You will design validation plans, analyze margins, and coordinate across silicon, firmware, and design teams.

You will build automated validation frameworks using Python/C/C++, perform eye diagram analysis, jitter measurements, and VREF optimization, ensuring release-ready silicon and robust test coverage.