System-Level Memory IP Validation Engineer

Synopsys Inc

Ottawa

On-site

CAD 110,000 - 150,000

Full time

14 days+

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

Synopsys Inc. is seeking a System Level Test Engineer in the Ottawa area to own memory interface IP validation (DDR, LPDDR, HBM) in the lab. You will bring up silicon, validate training, and characterize margins across PVT corners, with hands-on work on scopes, analyzers, and automated pipelines.

You will collaborate with firmware and design teams, write plans and reports, and support customer deployments. The role emphasizes rapid problem-solving and reproducible validation in a dialog with IP

Qualifications

Bachelor’s or Master’s in EE/CE or related field.
3–5 years in silicon validation or system-level lab debug of memory interfaces.
Hands-on silicon or board bring-up experience.
Working knowledge of DRAM protocol and training, JEDEC timing.

Responsibilities

Plan and execute system-level validation of DDR, LPDDR, and HBM IP on silicon across controller, PHY, and memory devices.
Bring up new silicon and reference platforms: power, clocks, reset, training, link-up, first read/write traffic.
Characterize data eye, timing, shmoo, and thermal corners; assess against JEDEC/IP specs.
Debug failures with oscilloscopes, analyzers, and on-chip status; track issues to closure.
Automate characterization pipelines using Gitlab for faster validation.
Write validation plans, test reports, and bug/errata entries for reproducibility.
Support customer system debug and feed lab findings into next IP drops.