Memory IP Hardware Validation Lead

Synopsys, Inc.; Ottawa; On-site; CAD 130,000 - 165,000; Full time

Job summary

Synopsys in Ottawa, Ontario seeks a senior hardware designer to validate memory-interface IP on boards and characterize high-speed interfaces. You will work in a lab-focused environment, bridging silicon behavior with real-world board performance.

You will analyze S-parameters, eye diagrams, and crosstalk, route JTAG/I2C/SPI/UART, and mentor engineers while contributing to design guidelines and faster bring-up of IP. This role is on-site in Nepean.

Qualifications

• Bachelor's or Master's in Electrical Engineering or equivalent hands-on experience.
• 6-8+ years in hardware design and validation for high-speed digital/mixed-signal systems.
• Expert Cadence Allegro proficiency for schematic capture and PCB layout.
• Deep knowledge of S-parameters, impedance, crosstalk, and return loss.
• Experience debugging with logic analyzers, oscilloscopes, VNAs, and spectrum analyzers.
• Experience with JTAG, I2C, SPI, UART interfaces and routing best practices.

Responsibilities

• Design, layout, and validate PCBs in Cadence Allegro for memory interface IP characterization.
• Analyze high-speed signal behavior using S-parameters, eye diagrams, and crosstalk simulations.
• Route and validate JTAG, I2C, SPI, and UART interfaces with attention to timing margins.
• Debug board-level issues using logic analyzers, oscilloscopes, and protocol analyzers.
• Review design files with cross-functional teams and teach routing and decoupling best practices.
• Interpret SPICE, IBIS, and channel analysis tool waveforms to validate analog/mixed-signal performance.
• Drive root cause analysis on validation failures spanning silicon, board, or environment.

Skills

Cadence Allegro

Signal integrity

High-speed digital

PCB layout

JTAG/I2C/SPI/UART

Bench instrumentation

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Allegro

Job description

Synopsys in Ottawa, Ontario seeks a senior hardware designer to validate memory-interface IP on boards and characterize high-speed interfaces. You will work in a lab-focused environment, bridging silicon behavior with real-world board performance.

You will analyze S-parameters, eye diagrams, and crosstalk, route JTAG/I2C/SPI/UART, and mentor engineers while contributing to design guidelines and faster bring-up of IP. This role is on-site in Nepean.