Senior Analog Design Architect – High-Speed IP

Synopsys, Inc.; Markham; On-site; CAD 120,000 - 180,000; Full time

Job summary

Synopsys, Inc. is seeking a senior analog/mixed-signal IC design engineer to advance high-speed CIRCUITS in FinFET nodes.

You will review JEDEC standards, define sub-block specs for DDR/LPDDR, HBM, UCIe, and mobile storage IP, and design transistor-level circuits with a focus on reliability and performance. Ideal candidates hold a PhD with extensive experience or a Master’s with substantial industry background.

Qualifications

• PhD with 6+ years or Master with 8+ years in analog and mixed-signal IC design.
• Deep CMOS transistor-level design with solid device physics understanding.
• Experience with high-speed analog sub-circuits and ESD techniques.

Responsibilities

• Review JEDEC standards to define analog and mixed-signal sub-block specs for DDR/LPDDR, HBM, UCIe, and mobile storage PHY IP.
• Design transistor-level circuits including equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgap references, ADCs and DACs.
• Develop verification strategies using SPICE simulators and Verilog-A models for coverage across PVT corners.
• Collaborate with layout engineers to minimize parasitics and manage device stress.
• Present simulation data and design tradeoffs to internal teams and customers.
• Document circuit designs, test plans, and reliability considerations for tape-out.

Skills

Analog circuit design

CMOS design

FinFET process

SPICE simulation

Verilog-A models

Python scripting

Education

PhD in Electrical Engineering

Master’s in Electrical Engineering

Tools

SPICE simulators (Spectre, HSPICE)

Schematic entry tools

Verilog-A

Job description

Synopsys, Inc. is seeking a senior analog/mixed-signal IC design engineer to advance high-speed CIRCUITS in FinFET nodes.

You will review JEDEC standards, define sub-block specs for DDR/LPDDR, HBM, UCIe, and mobile storage IP, and design transistor-level circuits with a focus on reliability and performance. Ideal candidates hold a PhD with extensive experience or a Master’s with substantial industry background.