Senior Staff ASIC Digital Design Lead — SERDES PHY IP

Synopsys, Inc.; Mississauga; On-site; CAD 120,000 - 180,000; Full time

Job summary

Synopsys, Inc. is seeking a visionary engineering leader to drive SERDES PHY IP design from concept to productization. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver cutting-edge silicon IP solutions.

The role emphasizes optimizing timing, performance, and power across multiple design cycles, mentoring engineers, and guiding customers through IP integration into SoCs while upholding industry-leading quality and reliability.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering.
• 8+ years of complex technical development experience.
• Proficiency in modeling, synthesizable Verilog and SystemVerilog design concepts and implementation.
• Strong front-end design flows: linting, synthesis, static timing analysis, CDC/RDC, DFT, and power optimization.
• Excellent communication skills and the ability to work independently and collaboratively.
• Understanding the PCIe and Ethernet standards is a plus.

Responsibilities

• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
• Planning, scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support.
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
• Mentoring and developing team members, fostering technical growth, and a culture of innovation.
• Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

Skills

Verilog

SystemVerilog

Front-end flows

Mentoring & leadership

Communication skills

Education

Bachelor's degree in Electrical Engineering

Tools

Synthesis tools

STA tools

Job description

Synopsys, Inc. is seeking a visionary engineering leader to drive SERDES PHY IP design from concept to productization. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver cutting-edge silicon IP solutions.

The role emphasizes optimizing timing, performance, and power across multiple design cycles, mentoring engineers, and guiding customers through IP integration into SoCs while upholding industry-leading quality and reliability.