Senior SERDES Verification Lead

Synopsys, Inc.; Mississauga; On-site; CAD 180,000 - 240,000; Full time

Benefits offered by this job

Health benefits and family coverage

Competitive compensation and rewards

Job summary

Synopsys, Inc. in Mississauga is seeking a senior verification leader for SERDES PHY IP. You will lead a distributed team of verification engineers and senior leads, driving sign-off quality while staying hands-on with waveform analysis and debugging.

You will mentor staff, set priorities, and ensure robust release evidence for high-performance SoCs. You will shape verification methodology, coordinate cross-functional partners across analog/digital design, firmware, and applications, and advance

Qualifications

• 10+ years in ASIC mixed-signal verification
• 3+ years leading verification engineers or teams
• Deep experience with PCIe and/or Ethernet SERDES
• Strong command of SystemVerilog, UVM, and coverage-driven verification
• Proficient in Shell, Perl, Python, or C++ for automation

Responsibilities

• Lead and grow a distributed team of verification engineers and senior technical leads
• Debug priority regressions, customer escalations, and silicon issues
• Own verification sign-off quality and release readiness for SERDES PHY IP
• Define and evolve UVM and mixed-signal co-simulation methodology
• Partner with analog/digital design, firmware, and applications teams to resolve blockers
• Represent verification in program reviews and cross-functional release planning
• Drive automation and AI-assisted regression triage to improve throughput and coverage

Skills

SystemVerilog

UVM

VIP integration

Coverage-driven verification

Scripting (Shell/Perl/Python/C++)

Leadership & mentoring

Team leadership

Tools

Verdi

DVE

Co-simulation tools

Job description

Synopsys, Inc. in Mississauga is seeking a senior verification leader for SERDES PHY IP. You will lead a distributed team of verification engineers and senior leads, driving sign-off quality while staying hands-on with waveform analysis and debugging.

You will mentor staff, set priorities, and ensure robust release evidence for high-performance SoCs. You will shape verification methodology, coordinate cross-functional partners across analog/digital design, firmware, and applications, and advance