Senior SoC RTL Design Engineer | Hybrid AI Chips

Tenstorrent Unlisted/Referral Jobs; Toronto; Hybrid; CAD 130,000 - 180,000; Full time

Job summary

Tenstorrent is seeking a Staff Digital Design Engineer to shape high-performance IP blocks and SoC architectures for AI workloads. The role blends microarchitecture, RTL implementation, and performance-aware design in a hybrid setting.

Ideal candidates will have architecture experience, Verilog/VHDL proficiency, and comfort with ASIC flows. You will collaborate across teams to push power, performance, and area efficiency while contributing to validation and backend readiness.

Qualifications

• Proven experience in digital design and microarchitecture.
• Experience with RTL development and ASIC flows.
• Strong ability to optimize for power, performance and area (PPA).
• Collaborative engineer comfortable with design reviews and cross-team planning.

Responsibilities

• Architect and implement Tenstorrent's IP blocks and SoC components.
• Drive RTL implementation and integration for high-performance compute workloads.
• Support validation via emulation, FPGA prototyping, or UVM flows when needed.
• Ensure timing closure and synthesis quality to back-end teams.

Skills

Digital design

RTL Development

Power optimization

Collaboration

Education

BS in Electrical Engineering

Tools

Verilog/VHDL

ASIC flows

Job description

Tenstorrent is seeking a Staff Digital Design Engineer to shape high-performance IP blocks and SoC architectures for AI workloads. The role blends microarchitecture, RTL implementation, and performance-aware design in a hybrid setting.

Ideal candidates will have architecture experience, Verilog/VHDL proficiency, and comfort with ASIC flows. You will collaborate across teams to push power, performance, and area efficiency while contributing to validation and backend readiness.