Hardware Intern - AI HW & System on a Chip

Tenstorrent; Ottawa; On-site; CAD 90,000 - 120,000; Full time

Job summary

Tenstorrent is seeking contributors at various seniorities for hardware architecture and AI hardware & SoC work. You will help define system, CPU, memory and interconnect decisions, verify integration, and ensure silicon-ready designs.

The role spans architecture, RTL, and performance modeling with collaboration across multiple teams. You will learn to translate specifications into RTL, evaluate architectural tradeoffs with data, and work with cross-functional teams to deliver high-performance

Qualifications

• Pursuing BS, MS, or PhD in EE/ECE/CE/CS with strong project work.
• Experience with digital design, architecture and performance modeling.
• Willingness to own and deliver on AI hardware projects.

Responsibilities

• Participate in SoC-level architecture and fabric/interconnect design decisions.
• Contribute to RTL design, verification, and timing analysis.
• Model performance and power for AI workloads and systems.
• Collaborate across Architecture, RTL, Software and Physical Design teams.

Skills

Python

C/C++

RTL design

Performance modeling

Education

BS/MS/PhD in EE/ECE/CE/CS

Tools

RISC-V

FPGA

ASIC design tools

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Overview: Before a single transistor gets placed, someone has to decide what the chip should actually be and ensure it functions to specs. This team makes those calls including System on a Chip (SoC)-level architecture, fabric/interconnect design, verification and not just core compute.

What you might work on: This posting spans multiple teams within Hardware Architecture & AI Hardware and SoC . One application, one recruiter screen - then we match you to the specific team and location that fits best. What each team does:

• Architecture: We define and evaluate the system, CPU, memory, fabric, and chiplet-level decisions that shape future products. We analyze workloads, performance, power, and system requirements, develop architectural models, do tradeoff analyses, and specifications for implementation.
• AI Hardware: We design and develop the core AI accelerator IP, including compute, data movement, and other specialized hardware blocks that enable high-performance AI workloads. We take these IPs from requirements through RTL design, verification, and delivery for SoC integration.
• SOC : Our team is where everything comes together. We design and verify the integration of all subsystems and the final pieces that allow the chip to interact with the outside world; scaleout, memory and on-chip system management and security. We validate cross functional and performance requirements, and ultimately take the design to silicon.

Who You Are

• Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS.
• Coursework or projects in digital design, computer architecture and performance modeling.
• Self-starter who brings sound judgment and practical problem-solving to every project with a solid interest in AI and hardware, along with the ability to take ownership and deliver results.

What We Need

• Familiarity with ASIC design concepts, ranging from performance simulations, RTL design / verification, and logic synthesis / timing analysis
• Scripting & programming skills (example: Python, PERL, tcl, C/C++); with experience using AI coding platforms
• [Architecture] Experience with architectural simulators.
• Exposure to RISC-V or other open ISAs is nice to have.
• FPGA design experience is nice to have.

What You Will Learn

• Taking designs from specification to RTL to verification, and learning the qualification checks and tools needed to do so.
• How architectural tradeoffs (Architecture: Compute vs. memory vs. interconnect. AI HW/ SOC: Power, Performance & Area) get decided with data, not intuition.
• Best practices for cross-functional collaboration, seeing firsthand how Architecture, RTL, Software, and Physical Design teams stay aligned through implementation.
• Practical methods to integrate AI tools directly into your daily technical workflow.
• [Architecture] Performance modeling methodology used before RTL existed.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.