Intermediate/Senior Digital IC Design Engineer

INNOSILICON; Ottawa; On-site; CAD 90,000 - 140,000; Full time

Job summary

INNOSILICON is seeking an Intermediate/Senior Digital IC Design Engineer to join our Inter-connectivity Memory Business Unit. You will collaborate with a global engineering team to develop SerDes IP products and ensure quality through rigorous design, verification, and production processes.

The role requires 5 years of relevant digital IC design experience, strong RTL in Verilog/SystemVerilog, and deep knowledge of ASIC tools and flows.

Qualifications

• Proactive, curious and eager to learn, great attention to details, positive, and great team work
• Bachelor's or Master's Degree in Electrical or Computer Engineering
• 5 years of relevant digital FPGA/ASIC/IC design experience
• Significant experience with RTL coding in Verilog/SystemVerilog
• Significant experience with standard ASIC software tools (lint, clock domain crossing analysis, timing constraints, synthesis, simulation, logical equivalence checking, DFT, static timing analysis)
• Strong knowledge of Python scripting, Linux/Unix environment, and basic C/C++ programming
• Strong knowledge of PCIe, Ethernet
• Thorough understanding of ASIC design flow
• Design-for-verification experience or understanding (assertion-based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
• Self-starter and fast learner with excellent interpersonal skills
• Track record of driving technical solutions across organizational boundaries and multiple technical disciplines
• Proficiency in Chinese would be considered an asset

Responsibilities

• Design specification: Help write block-level design specifications, run system-level simulations, and support chip-level architecture definition and documentation.
• Implementation: Develop RTL in Verilog and take blocks through lint, clock domain crossing (CDC) analysis, synthesis, static timing analysis, timing closure, and top-level integration. Support DFT tasks.
• Verification: Work with the verification team on test planning and execution, debug block- and system-level simulations, and support formal verification.
• Flow and methodology: Help develop and improve the design flows and methods used across our interdisciplinary R&D group.
• Validation and production: Work with the validation and production teams to create test plans and test vectors that ensure product quality and robustness.

Skills

RTL Verilog/SystemVerilog

Python scripting

Linux/Unix

C/C++ programming

PCIe & Ethernet knowledge

Digital IC/ASIC/FPGA design

Teamwork & communication

Self-starter

Chinese language

Education

Bachelor's or Master's Degree in Electrical or Computer Engineering

Tools

ASIC tools suite (lint, CDC analysis, timing constraints, synthesis, simulation, E/QC, DFT, STA)

Job description

Innosilicon is seeking to hire an Intermediate/Senior Digital IC Design Engineer to join our Inter-connectivity Memory Business Unit. The successful candidate will work with our experienced global engineering team developing market-leading SerDes IP products.We look forward to welcoming talented engineers on our journey.

Responsibilities

• Design specification: Help write block-level design specifications, run system-level simulations, and support chip-level architecture definition and documentation.
• Implementation: Develop RTL in Verilog and take blocks through lint, clock domain crossing (CDC) analysis, synthesis, static timing analysis, timing closure, and top-level integration. Support DFT tasks.
• Verification: Work with the verification team on test planning and execution, debug block- and system-level simulations, and support formal verification.
• Flow and methodology: Help develop and improve the design flows and methods used across our interdisciplinary R&D group.
• Validation and production: Work with the validation and production teams to create test plans and test vectors that ensure product quality and robustness.

Qualifications

• Proactive, curious and eager to learn, great attention to details, positive, and great team work
• Bachelor's or Master's Degree in Electrical or Computer Engineering
• 5 years of relevant digital FPGA/ASIC/IC design experience
• Significant experience with RTL coding in Verilog/SystemVerilog
• Significant experience with standard ASIC software tools (lint, clock domain crossing analysis, timing constraints, synthesis, simulation, logical equivalence checking, DFT, static timing analysis)
• Strong knowledge of Python scripting, Linux/Unix environment, and basic C/C++ programming
• Strong knowledge of PCIe, Ethernet
• Thorough understanding of ASIC design flow
• Design-for-verification experience or understanding (assertion-based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
• Self-starter and fast learner with excellent interpersonal skills
• Track record of driving technical solutions across organizational boundaries and multiple technical disciplines
• Proficiency in Chinese would be considered an asset