Senior SoC Design Engineer - RTL/ASIC, Low Power

Qualcomm; Vancouver; On-site; CAD 181,000 - 251,000; Full time

Job summary

Qualcomm Canada ULC is seeking an experienced ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP for high‑performance, low‑power SoCs. You will collaborate with cross‑functional teams across the US and India to determine the product execution path and ensure quality across the full development cycle.

The role requires strong RTL coding in Verilog/VHDL/SV, experience with UPF power domains, and familiarity with bus protocols such

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 4+ years ASIC design/verification experience.
• Master's degree in Science, Engineering, or related field with 3+ years ASIC design/verification experience.
• PhD in Science, Engineering, or related field with 2+ years ASIC design/verification experience.

Responsibilities

• Digital design and development (RTL) across multi-site leads in US and India.
• Develop micro architecture and implement design using Verilog/SV; deliver complex subsystem to SoC.
• Define tasks and deliver independently.
• Coordinate with Systems, Verification, SoC, SW, PD & DFT teams to achieve goals.
• Analyze reports/waivers and run tools: Spyglass, 0-in, DC-Compiler, PrimeTime, synthesis, simulation.

Skills

ASIC design

RTL coding

Verilog/VHDL/SV

Power domain crossing

Spyglass Lint/CDC

Formal verification

Perl

TCL

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Cadence LEC

Spyglass

DC-Compiler

PrimeTime

Verilog

VHDL

SV

Verilog/SystemVerilog

Job description

Qualcomm Canada ULC is seeking an experienced ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP for high‑performance, low‑power SoCs. You will collaborate with cross‑functional teams across the US and India to determine the product execution path and ensure quality across the full development cycle.

The role requires strong RTL coding in Verilog/VHDL/SV, experience with UPF power domains, and familiarity with bus protocols such