Senior High-Speed Analog Layout Engineer – IP Blocks Lead

Celero Communications, Inc.; Ottawa; On-site; CAD 150,000 - 230,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal High-Speed Analog Layout Design Engineer to lead the layout of complex analog/mixed-signal IP blocks for next‑gen optical communication systems in Ottawa.

You will mentor junior engineers and collaborate with CAD/PDK teams to ensure first‑pass silicon success. In this hands‑on role, you will drive floorplanning, LVS/DRC checks, and layout verification using industry tools, while guiding cross‑functional teams across time zones and contributing

Qualifications

• 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
• Proven track record of top-level integration IP layout macros or full-chip layout at FinFET nodes
• Experience leading IP layout macros or full-chip layouthandoff to Physical Design

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through verification
• Collaborate with schematic designers to optimize layouts for performance, matching, symmetry and reliability
• Mentor junior layout engineers and contractors across multiple time zones
• Perform LVS, DRC, PERC, ERC and signoff checks using industry-standard tools
• Contribute to chip-level planning including top-level floor planning and power grid design
• Lead layout design reviews and set layout quality and schedule expectations
• Support automation initiatives through scripting (Python/TCL) and tool customization

Skills

Analog layout

Mixed-signal

Cadence Virtuoso

LVS/DRC

Floor planning

Mentoring

Power integrity

Layout verification

Python scripting

Tools

Calibre

Pegasus

Job description

Celero Communications, Inc. is seeking a Principal High-Speed Analog Layout Design Engineer to lead the layout of complex analog/mixed-signal IP blocks for next‑gen optical communication systems in Ottawa.

You will mentor junior engineers and collaborate with CAD/PDK teams to ensure first‑pass silicon success. In this hands‑on role, you will drive floorplanning, LVS/DRC checks, and layout verification using industry tools, while guiding cross‑functional teams across time zones and contributing