Senior PLL Design Architect for High-Speed Transceivers

Celero Communications, Inc.; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal PLL Design Engineer in Ottawa to drive high-speed clocking design for next‑gen optical transceivers and SerDes.

The role focuses on designing and validating PLLs, VCOs and related analog blocks in advanced CMOS nodes, with hands-on lab bring-up and system-level validation. The ideal candidate has a Master’s or PhD in EE with 5+ years in PLL design, proficiency in Cadence Virtuoso and MATLAB, and strong documentation and cross‑functional

Qualifications

• Master’s or PhD in Electrical Engineering required.
• 5+ years of PLL design experience with production tape-out exposure.
• Experience with advanced node processes (e.g., 16nm/12nm, 7nm, 5nm, 3nm, 2nm).

Responsibilities

• Architect, design and simulate analog/mixed-signal PLL blocks (VCOs, charge pumps, dividers, PFDs, loop filters).
• Analyze PLL topologies to meet power, area, jitter, and frequency specs.
• Supervise layouts for floorplanning, matching, and parasitic minimization.
• Bring up PLLs in lab and characterize performance with modern lab equipment.
• Conduct system-level simulations for PLL integration in transceivers.

Skills

PLL Design

Phase Noise Analysis

VCO Design

Documentation

Education

Master’s or PhD in Electrical Engineering

Tools

Cadence Virtuoso

EMX/HFSS

MATLAB

Job description

Celero Communications, Inc. is seeking a Principal PLL Design Engineer in Ottawa to drive high-speed clocking design for next‑gen optical transceivers and SerDes.

The role focuses on designing and validating PLLs, VCOs and related analog blocks in advanced CMOS nodes, with hands-on lab bring-up and system-level validation. The ideal candidate has a Master’s or PhD in EE with 5+ years in PLL design, proficiency in Cadence Virtuoso and MATLAB, and strong documentation and cross‑functional