Senior FPGA Engineer: High-Performance IO & RDMA

Cerebras

Toronto

On-site

CAD 120,000 - 160,000

Full time

8 days ago
Application generator

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Job summary

Cerebras Systems, Toronto-based, is seeking an FPGA developer for the Host and Network IO Team. You will own the in-chassis IO subsystem, including RoCE v2 interfaces, a large programmable switching fabric, and a proprietary Cerebras IO protocol, supporting AI workloads on the WSE.

You will collaborate with AI application IO teams, cluster architecture, and embedded software to optimize bandwidth and latency across generations of hardware and future architectures.

Qualifications

  • 5+ years of FPGA development experience in production systems.
  • Masters/PhD in Computer or Electrical Engineering plus 3+ years industry experience.
  • Proficiency in Verilog and Git-based workflows.

Responsibilities

  • Lead full chassis-to-wafer IO architecture and design.
  • Improve RTL, implement next-gen FPGA design, define future IO architectures.
  • Produce production-ready bitstreams for deployment into large clusters.
  • Work with DV team to prevent bug slips and simplify debugging.
  • Optimize bandwidth/latency over FPGA datapath and all IO interfaces.
  • Interface with board team facilitating and executing board bring-up.
  • Drive network performance debug of large AI clusters.
  • Integrate leading edge networking technologies and protocols.
  • Lead cross-functional technical projects spanning multiple teams and integrating software and hardware.
  • Foster clear and effective communication across teams and stakeholders.

Skills

FPGA development
Verilog
FPGA placement & routing
Network protocols (TCP/RoCE)
Network debugging
AI-augmented development

Education

Master's or PhD in Computer or Electrical Engineering

Tools

Git
Wireshark
Arista/Juniper switching knowledge

Job description

Cerebras Systems, Toronto-based, is seeking an FPGA developer for the Host and Network IO Team. You will own the in-chassis IO subsystem, including RoCE v2 interfaces, a large programmable switching fabric, and a proprietary Cerebras IO protocol, supporting AI workloads on the WSE.

You will collaborate with AI application IO teams, cluster architecture, and embedded software to optimize bandwidth and latency across generations of hardware and future architectures.

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