Senior FPGA Engineer: High-Speed AI IO & RDMA

Foundation Capital; Toronto; On-site; CAD 120,000 - 180,000; Full time

Job summary

Cerebras Systems seeks an experienced FPGA developer to own the in-chassis IO subsystem, including RoCE interfaces, a large programmable switching fabric, and the Cerebras WSE communication protocol. You will optimize bandwidth and latency for multi-node AI clusters and deliver production‑ready solutions.

You will collaborate with AI application IO teams, cluster architecture, and embedded software groups across hardware and software boundaries to enable scalable, high‑speed inference and

Qualifications

• 5+ years producing production FPGA solutions.
• Proficiency in Verilog development in Git-based repo.
• Experience with FPGA placement, routing, timing closure, and debugging.
• Familiarity with TCP and RoCE networks.
• Experience with network switch environments (Arista, Juniper) or willingness to learn.
• AI-augmented development environment experience preferred.

Responsibilities

• Lead full chassis-to-wafer IO architecture and design
• Improve current RTL, implement next-gen FPGA design, define future IO architectures
• Produce production-ready bitstreams for deployment into large clusters running customer inference services
• Work with DV team to prevent bug slips and simplify debug
• Optimize bandwidth/latency over FPGA datapath and all IO interfaces
• Interface with board team facilitating and executing board bringup
• Drive network performance debug of large AI clusters
• Integrate leading edge networking technologies and protocols
• Lead cross-functional technical projects spanning multiple teams and integrating diverse software and hardware components to deliver an improved network IO solution.
• Foster clear and effective communication across teams and stakeholders.

Skills

FPGA design

Verilog

Networking protocols

Git-based workflow

Timing closure

Debugging/Simulation

AI/ML hardware

Education

Master's or PhD in Computer or Electrical Engineering

Bachelor's degree in Computer or Electrical Engineering

Tools

Git

FPGA placement & routing tools

Wireshark

RoCE troubleshooting

Job description

Cerebras Systems seeks an experienced FPGA developer to own the in-chassis IO subsystem, including RoCE interfaces, a large programmable switching fabric, and the Cerebras WSE communication protocol. You will optimize bandwidth and latency for multi-node AI clusters and deliver production‑ready solutions.

You will collaborate with AI application IO teams, cluster architecture, and embedded software groups across hardware and software boundaries to enable scalable, high‑speed inference and