Senior Design Verification Engineer

CYNET SYSTEMS; Ottawa; On-site; CAD 80,000 - 100,000; Full time

Job summary

A leading company in Ottawa is seeking a skilled verification engineer to develop and maintain functional tests using UVM. The ideal candidate will have substantial experience in C/C++, System Verilog, and verification methodologies. This role involves leading IPs and providing technical support across teams, ensuring high-quality verification processes for next-generation IP. If you have a Bachelor's or Master's degree in engineering and a passion for cutting-edge technology, we want to hear from you!

Qualifications

• 5+ years' experience required.
• Exposure to AXI protocol and Boot code Verification.

Responsibilities

• Develop/Maintain tests for functional verification with UVM.
• Build test bench components for next generation IP.
• Provide technical support to other teams.

Skills

C/C++

System Verilog

UVM

Scripting

Education

Bachelors in Computer Engineering

Masters in Electrical Engineering

Job description

Job Description: Responsibilities:

• Develop/Maintain tests for functional verification with UVM verification at the subsystem level.
• Build test bench components to support the next generation IP.
• Maintain or improve current test libraries to support IP level testing.
• Technically lead IPs in Control Fabric.
• Have exposure to AXI protocol and Boot code Verification.
• Provide technical support to other teams.

Preferred Experience:

• 5+ years' experience required.
• Good at C/C++.
• Good at SV and UVM.
• Good scripting knowledge in Perl, Ruby and Make file.
• Familiarity with System Verilog and modern verification libraries like UVM.

Academic Credentials:

• Bachelors (required) or Masters degree in computer engineering/Electrical Engineering.