Senior Digital Verification Engineer

TSMC; Eastern Ontario; On-site; CAD 80,000 - 130,000; Full time

Job summary

An established industry player in semiconductor manufacturing is seeking a talented Digital Verification Engineer. In this pivotal role, you will collaborate with design teams to validate digital circuits, develop advanced test benches, and enhance EDA capabilities. This position offers a unique opportunity to work on cutting-edge technology challenges while contributing to the innovation of digital verification methodologies. If you possess a strong background in digital verification and thrive in a dynamic environment, this role is perfect for you, offering a chance to make a significant impact in the semiconductor field.

Qualifications

• 8+ years of experience in digital verification within the semiconductor industry.
• Proficiency in logic and timing simulation using Verilog simulation tools.

Responsibilities

• Validate digital circuit implementations and develop test benches.
• Contribute to the customization of digital verification methodologies.

Skills

Digital Verification

Verilog Simulation

SystemVerilog

Unix/Linux

Problem Solving

Communication Skills

Education

Master's degree in Electrical/Computer Engineering

Tools

VCS

NCVerilog

SPICE Simulation Tools

Job description

1 week ago Be among the first 25 applicants

Get AI-powered advice on this job and more exclusive features.

Position Located in: Ottawa, Ontario, Canada Design Center, Kanata High Tech Park

TSMC Design Technology Canada Inc. is looking for a full-time, experienced, and advanced Digital Verification Engineer who is currently located within North America and meets the current immigration requirements to work in Canada.

The Senior Digital Verification Engineer will work closely with design teams to validate digital circuit implementations, develop test benches, perform functional verification, prepare manufacturing/tester patterns, and debug failing tests. The successful candidate will also contribute to the customization of standard digital verification methodologies and help improve the electronic design automation (EDA) capabilities of the group.

Qualifications:

1. Master's degree or higher in Electrical/Computer Engineering or related field, or an equivalent combination of education and experience.
2. 8+ years of experience in digital verification within the semiconductor industry.
3. Experience in large-scale chip design and sign-off processes.
4. Knowledge of nano-scale technology issues and challenges.
5. Experience with Universal Verification Methodology (UVM) development.
6. Proficiency in logic and timing simulation using Verilog simulation tools (VCS, NCVerilog).
7. Experience writing and debugging simulation test benches and tools, with proficiency in SystemVerilog, SV assertions, system-level verification planning, methodologies, and debugging tools.
8. Working knowledge of Unix/Linux operating systems and scripting languages.
9. Strong problem-solving and analytical skills.
10. Excellent verbal and written communication skills.
11. Proven ability to work effectively both independently and in a team environment.
12. Experience with code and functional coverage, and formal verification is a plus.

Assets:

1. Experience in circuit-level verification using SPICE simulation tools.
2. Ability to work well with teams in diverse locations.
3. Experience with Design for Test techniques, implementation, and verification.

Send a cover letter (quoting Senior Digital Verification Engineer) and your resume in confidence to:

Sandee Kimmons

Sr HR Business Partner

TSMC Design Technology Canada Inc.

[e-mail]

Note: this is not a New Grad position.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Industries

• Semiconductor Manufacturing