Senior Design Verification Engineer

Cynet Systems Inc; Ottawa; On-site; CAD 80,000 - 100,000; Full time

Job summary

A leading technology firm in Ottawa is seeking a skilled Verification Engineer to develop and maintain tests for functional verification using UVM. The ideal candidate will have extensive experience with C/C++, System Verilog, and modern verification libraries. Responsibilities include leading IPs in Control Fabric and supporting other teams with technical expertise. This role offers the opportunity to work on cutting-edge technology and contribute to the development of next-generation IP.

Qualifications

• 5+ years' experience required.
• Good at C/C++, SV, UVM, and scripting.

Responsibilities

• Develop/Maintain tests for functional verification with UVM.
• Build test bench components for next generation IP.
• Provide technical support to other teams.

Skills

C/C++

Scripting

UVM

System Verilog

Education

Bachelors in Computer Engineering

Masters in Electrical Engineering

Job description

Job Description:

Responsibilities:

• Develop/Maintain tests for functional verification with UVM verification at the subsystem level.
• Build test bench components to support the next generation IP.
• Maintain or improve current test libraries to support IP level testing.
• Technically lead IPs in Control Fabric.
• Have exposure to AXI protocol and Boot code Verification.
• Provide technical support to other teams.

Preferred Experience:

• 5+ years' experience required.
• Good at C/C++.
• Good at SV and UVM.
• Good scripting knowledge in Perl, Ruby and Make file.
• Familiarity with System Verilog and modern verification libraries like UVM.

Academic Credentials:

• Bachelors (required) or Masters degree in computer engineering/Electrical Engineering.