Design Verification Engineer - Senior (CAN)

Mindlance; Ottawa; On-site; CAD 80,000 - 100,000; Full time

Job summary

A leading technology company in Ottawa seeks a self-motivated Design Verification Engineer to enhance their verification processes. The successful candidate will develop tests, lead verification efforts, and collaborate across teams to ensure high-quality technology delivery. Ideal candidates will have a strong background in processor architecture and digital design.

Qualifications

• Minimum 5 years of relevant experience.
• Proficiency in C/C++, SystemVerilog, and UVM.

Responsibilities

• Develop and maintain tests for functional verification using UVM.
• Lead the verification of Control Fabric IPs.
• Provide technical support to other teams.

Skills

Analytical Skills

Problem Solving

Communication

Education

Bachelor's degree in computer engineering

Master's degree

Tools

C/C++

SystemVerilog

UVM

Perl

Ruby

Makefile

Job description

THE ROLE:

We are looking for an adaptive, self-motivated design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team fosters continuous technical innovation and supports career development.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification. You are a team player with excellent communication skills and experience collaborating across different sites and time zones. You possess strong analytical and problem-solving skills and are eager to learn and tackle new challenges.

KEY RESPONSIBILITIES:

1. Develop and maintain tests for functional verification using UVM at the subsystem level.
2. Build testbench components for the next-generation IP.
3. Maintain or improve current test libraries for IP-level testing.
4. Lead the verification of Control Fabric IPs.
5. Gain exposure to AXI protocol and Bootcode verification.
6. Provide technical support to other teams.

PREFERRED EXPERIENCE:

• Minimum 5 years of relevant experience.
• Proficiency in C/C++.
• Knowledge of SystemVerilog and UVM.
• Scripting skills in Perl, Ruby, and Makefile.
• Familiarity with modern verification libraries like UVM.

ACADEMIC CREDENTIALS:

Bachelor's degree in computer engineering or electrical engineering is required; a Master's degree is a plus.

EEO:

Mindlance is an Equal Opportunity Employer and does not discriminate based on minority, gender, disability, religion, LGBTQI status, age, or veteran status.