Design Verification Engineer - Senior (CAN)

LanceSoft Inc; Ottawa; On-site; CAD 80,000 - 100,000; Full time

Job summary

A growing tech company in Ottawa seeks a Design Verification Engineer to join their team. The ideal candidate will have a passion for processor architecture and verification, with strong analytical skills. Responsibilities include developing tests for functional verification and leading IPs in Control Fabric. Candidates should have experience with UVM, SystemVerilog, and C/C++. A Bachelor's degree in Computer or Electrical Engineering is required.

Qualifications

• 5+ years of relevant experience.
• Proficiency in C/C++.

Responsibilities

• Develop and maintain tests for functional verification with UVM.
• Build testbench components to support the next generation IP.
• Provide technical support to other teams.

Skills

UVM

SystemVerilog

C

C++

Education

Bachelor's in Computer Engineering

Master's in Electrical Engineering

Tools

Perl

Ruby

Makefile

Job description

Top priority skills: UVM, SystemVerilog, C, C++

THE ROLE:

We are looking for an adaptive, self-motivated design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player with excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You possess strong analytical and problem-solving skills and are willing to learn and take on challenges.

KEY RESPONSIBILITIES:

1. Develop and maintain tests for functional verification with UVM verification at the subsystem level.
2. Build testbench components to support the next generation IP.
3. Maintain or improve current test libraries to support IP level testing.
4. Technically lead IPs in Control Fabric.
5. Gain exposure to AXI protocol and Bootcode Verification.
6. Provide technical support to other teams.

PREFERRED EXPERIENCE:

1. 5+ years of relevant experience.
2. Proficiency in C/C++.
3. Experience with SystemVerilog and UVM.
4. Good scripting knowledge in Perl, Ruby, and Makefile.
5. Familiarity with SystemVerilog and modern verification libraries like UVM.

ACADEMIC CREDENTIALS:

Bachelor's (required) or Master's degree in Computer Engineering or Electrical Engineering.