Senior Low-Power AI ASIC Verification Lead

QUALCOMM, Inc.; Markham; On-site; CAD 108,000 - 180,000; Full time

Job summary

Qualcomm Canada ULC is seeking a senior ASIC verification engineer to shape the verification strategy for next-gen ASICs in the ASICS Engineering group. You will contribute to pre/post-silicon verification, write testbenches, and drive coverage with scalable flows.

Required expertise includes SystemVerilog, UVM, SystemC, and HDLs; 2+ years in ASIC design/verification; strong debugging and leadership abilities in a fast-paced, cutting-edge environment in Canada.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 4+ years ASIC experience.
• Master's degree in Science, Engineering, or related field with 3+ years ASIC experience.
• PhD in Science, Engineering, or related field with 2+ years ASIC experience.
• 2+ years ASIC design, verification, implementation or related work experience

Responsibilities

• Contribute to core verification during the pre/post silicon phase of next generation ASICs through simulation.
• Drive test plan development, execution and verification closure in conjunction with the design and verification teams.
• Contribute to creating/maintaining a test bench, assertions, and functional coverage models with scalability and reuse as key goals.
• Contribute to implementing flows to automate development processes. Identify areas for improvement and drive them to completion.
• Lead complex debug activities through the development cycle (pre and post-silicon).
• Provide technical supervision to other engineers and have the ability to lead by example.
• Work closely with design to define verification methodology, Provide test plans and develop required tests.

Skills

Verilog/SystemVerilog

UVM/SystemC

ASIC/RTL design

C/C++

Debug & verification

Education

Bachelor's degree in Science or Engineering

Master's degree in Science or Engineering

PhD in Science or Engineering

Tools

SystemVerilog

UVM

SystemC

Job description

Qualcomm Canada ULC is seeking a senior ASIC verification engineer to shape the verification strategy for next-gen ASICs in the ASICS Engineering group. You will contribute to pre/post-silicon verification, write testbenches, and drive coverage with scalable flows.

Required expertise includes SystemVerilog, UVM, SystemC, and HDLs; 2+ years in ASIC design/verification; strong debugging and leadership abilities in a fast-paced, cutting-edge environment in Canada.